JPS5761350A - Automatic monitor system of circuit - Google Patents

Automatic monitor system of circuit

Info

Publication number
JPS5761350A
JPS5761350A JP55136118A JP13611880A JPS5761350A JP S5761350 A JPS5761350 A JP S5761350A JP 55136118 A JP55136118 A JP 55136118A JP 13611880 A JP13611880 A JP 13611880A JP S5761350 A JPS5761350 A JP S5761350A
Authority
JP
Japan
Prior art keywords
monitor device
slave
trouble
master
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55136118A
Other languages
Japanese (ja)
Inventor
Michihiro Ono
Yuji Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP55136118A priority Critical patent/JPS5761350A/en
Publication of JPS5761350A publication Critical patent/JPS5761350A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE:To monitor continuously a titled system even if trouble is generated on the master monitor device by using a slave monitor device, by installing a control section on the slave monitor device, which provides almost the same functions as the control section of the master monitor device. CONSTITUTION:Many kinds of commands are sent to each slave monitor device 21 and 22 from a personal computer (PC)11 of a master monitor device 1. The slave monitor device 21 and 22 measure according to the contents of command and sends the measured data to a device 1. In case, trouble is generated on the device 1 and the device can not control the device 21 and 22, a command from a PC24 of the device 21 is transmitted to the other slave monitor device 22. As described here, trouble is generated on the device 1, the slave monitor device operates as a master monitor device. Then, the circuit condition can continuously be monitored.
JP55136118A 1980-09-30 1980-09-30 Automatic monitor system of circuit Pending JPS5761350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55136118A JPS5761350A (en) 1980-09-30 1980-09-30 Automatic monitor system of circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55136118A JPS5761350A (en) 1980-09-30 1980-09-30 Automatic monitor system of circuit

Publications (1)

Publication Number Publication Date
JPS5761350A true JPS5761350A (en) 1982-04-13

Family

ID=15167716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55136118A Pending JPS5761350A (en) 1980-09-30 1980-09-30 Automatic monitor system of circuit

Country Status (1)

Country Link
JP (1) JPS5761350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63166324A (en) * 1986-12-26 1988-07-09 Anritsu Corp Line quality test system
US6339698B1 (en) * 1993-07-30 2002-01-15 British Telecommunications Public Limited Company Communications system with controlled selective measuring of traffic properties

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5372403A (en) * 1976-12-10 1978-06-27 Hitachi Ltd Loop communication system
JPS5471283A (en) * 1977-11-17 1979-06-07 Nec Corp Remote monitor control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5372403A (en) * 1976-12-10 1978-06-27 Hitachi Ltd Loop communication system
JPS5471283A (en) * 1977-11-17 1979-06-07 Nec Corp Remote monitor control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63166324A (en) * 1986-12-26 1988-07-09 Anritsu Corp Line quality test system
US6339698B1 (en) * 1993-07-30 2002-01-15 British Telecommunications Public Limited Company Communications system with controlled selective measuring of traffic properties

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