JPS5760732A - Dynamic signal generating circuit - Google Patents
Dynamic signal generating circuitInfo
- Publication number
- JPS5760732A JPS5760732A JP55134090A JP13409080A JPS5760732A JP S5760732 A JPS5760732 A JP S5760732A JP 55134090 A JP55134090 A JP 55134090A JP 13409080 A JP13409080 A JP 13409080A JP S5760732 A JPS5760732 A JP S5760732A
- Authority
- JP
- Japan
- Prior art keywords
- node
- circuit
- trt2
- potential
- trt4
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
Abstract
PURPOSE:To generate a dynamic signal which has less power consumption and has less influence upon fluctuation of a power source voltage, by boosting a clock signal input by a boosting circuit due to capacity coupling to generate a delayed clock signal output. CONSTITUTION:When the potential difference of a certain degree is generated between both ends of a capacitor C, a node N2 between a semiconductor circuit 1 and a transistor TRT2 is discharged. Then, the TRT2 and a TRT4 which has the base cascaded to the TRT2 are turned off, and the node N2 is charged from a low potential VL1 to a high potential. By capacity coupling due to the capacitor C, etc. between the node N2 and a node N1 between the circuit 1 and a TRT1, the node N1 is boosted and has a potential Vp higher than a power source voltage VDD. Thus, a clock input signal phi of the circuit 1 is supplied to a node N4 where the drain of the TRT4 and the source of a TRT5 are connected, and a delayed signal phid is outputted.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55134090A JPS5760732A (en) | 1980-09-26 | 1980-09-26 | Dynamic signal generating circuit |
DE8181107500T DE3174470D1 (en) | 1980-09-26 | 1981-09-21 | Dynamic signal generation circuit |
EP81107500A EP0048922B1 (en) | 1980-09-26 | 1981-09-21 | Dynamic signal generation circuit |
US06/304,592 US4472643A (en) | 1980-09-26 | 1981-09-22 | Dynamic signal generation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55134090A JPS5760732A (en) | 1980-09-26 | 1980-09-26 | Dynamic signal generating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5760732A true JPS5760732A (en) | 1982-04-12 |
Family
ID=15120183
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55134090A Pending JPS5760732A (en) | 1980-09-26 | 1980-09-26 | Dynamic signal generating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5760732A (en) |
-
1980
- 1980-09-26 JP JP55134090A patent/JPS5760732A/en active Pending
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