JPS575370B2 - - Google Patents

Info

Publication number
JPS575370B2
JPS575370B2 JP9400276A JP9400276A JPS575370B2 JP S575370 B2 JPS575370 B2 JP S575370B2 JP 9400276 A JP9400276 A JP 9400276A JP 9400276 A JP9400276 A JP 9400276A JP S575370 B2 JPS575370 B2 JP S575370B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9400276A
Other languages
Japanese (ja)
Other versions
JPS5333566A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9400276A priority Critical patent/JPS5333566A/ja
Publication of JPS5333566A publication Critical patent/JPS5333566A/ja
Publication of JPS575370B2 publication Critical patent/JPS575370B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096Synchronous circuits, i.e. using clock signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
JP9400276A 1976-08-09 1976-08-09 Low-power logical circuit Granted JPS5333566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9400276A JPS5333566A (en) 1976-08-09 1976-08-09 Low-power logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9400276A JPS5333566A (en) 1976-08-09 1976-08-09 Low-power logical circuit

Publications (2)

Publication Number Publication Date
JPS5333566A JPS5333566A (en) 1978-03-29
JPS575370B2 true JPS575370B2 (Direct) 1982-01-30

Family

ID=14098198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9400276A Granted JPS5333566A (en) 1976-08-09 1976-08-09 Low-power logical circuit

Country Status (1)

Country Link
JP (1) JPS5333566A (Direct)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574618A (en) * 1980-06-11 1982-01-11 Hitachi Ltd Flip-flop

Also Published As

Publication number Publication date
JPS5333566A (en) 1978-03-29

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