JPS575163A - Simulate-trouble generation system - Google Patents

Simulate-trouble generation system

Info

Publication number
JPS575163A
JPS575163A JP7798480A JP7798480A JPS575163A JP S575163 A JPS575163 A JP S575163A JP 7798480 A JP7798480 A JP 7798480A JP 7798480 A JP7798480 A JP 7798480A JP S575163 A JPS575163 A JP S575163A
Authority
JP
Japan
Prior art keywords
simulation
circuit
trouble
instruction
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7798480A
Other languages
Japanese (ja)
Other versions
JPS6113609B2 (en
Inventor
Koichi Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7798480A priority Critical patent/JPS575163A/en
Publication of JPS575163A publication Critical patent/JPS575163A/en
Publication of JPS6113609B2 publication Critical patent/JPS6113609B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To generate a program without depending upon hardware/firmware by forcibly setting operation conditions, when a simulation trouble is caused, independently of normal timing and by setting the simulation trouble directly without reference to the normal timing. CONSTITUTION:After a register 1 for simulation generation conditions is set, a simulated environment setting circuit 11 force an enabled/disabled retrying discriminating circuit to an enabled or disabled state. Then, a simulated timing forcible generating circuit 10 enables a decoder 2 and an error indicator 8 is set through an OR circuit 6 and an AND circuit 7, generating a simulation trouble in an instruction. When the instruction is retried, the instruction is completed without generating the simulation trouble for the 2nd time and later, and when retrying is assumed to be failed the simulation trouble is generated for the 2nd time or later.
JP7798480A 1980-06-10 1980-06-10 Simulate-trouble generation system Granted JPS575163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7798480A JPS575163A (en) 1980-06-10 1980-06-10 Simulate-trouble generation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7798480A JPS575163A (en) 1980-06-10 1980-06-10 Simulate-trouble generation system

Publications (2)

Publication Number Publication Date
JPS575163A true JPS575163A (en) 1982-01-11
JPS6113609B2 JPS6113609B2 (en) 1986-04-14

Family

ID=13649121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7798480A Granted JPS575163A (en) 1980-06-10 1980-06-10 Simulate-trouble generation system

Country Status (1)

Country Link
JP (1) JPS575163A (en)

Also Published As

Publication number Publication date
JPS6113609B2 (en) 1986-04-14

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