JPS5749468Y2 - - Google Patents
Info
- Publication number
- JPS5749468Y2 JPS5749468Y2 JP1980077269U JP7726980U JPS5749468Y2 JP S5749468 Y2 JPS5749468 Y2 JP S5749468Y2 JP 1980077269 U JP1980077269 U JP 1980077269U JP 7726980 U JP7726980 U JP 7726980U JP S5749468 Y2 JPS5749468 Y2 JP S5749468Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
Landscapes
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2420106A DE2420106A1 (de) | 1974-04-25 | 1974-04-25 | Schaltungsanordnung zum unterdruecken von binaersignalen ueberlagerten stoerimpulsen |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55173641U JPS55173641U (cs) | 1980-12-12 |
| JPS5749468Y2 true JPS5749468Y2 (cs) | 1982-10-29 |
Family
ID=5913957
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50049558A Pending JPS50149259A (cs) | 1974-04-25 | 1975-04-23 | |
| JP1980077269U Expired JPS5749468Y2 (cs) | 1974-04-25 | 1980-06-03 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50049558A Pending JPS50149259A (cs) | 1974-04-25 | 1975-04-23 |
Country Status (2)
| Country | Link |
|---|---|
| JP (2) | JPS50149259A (cs) |
| DE (1) | DE2420106A1 (cs) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2901340A1 (de) * | 1979-01-15 | 1980-07-24 | Vdo Schindling | Schaltungsanordnung zur erzeugung einer rechteckspannung |
| JPS56110333A (en) * | 1980-02-05 | 1981-09-01 | Fujitsu Ltd | Digital integral network |
| JPS58173927U (ja) * | 1982-05-17 | 1983-11-21 | 富士通テン株式会社 | ロ−バスフイルタ |
| JPH01156633U (cs) * | 1989-03-02 | 1989-10-27 |
-
1974
- 1974-04-25 DE DE2420106A patent/DE2420106A1/de active Pending
-
1975
- 1975-04-23 JP JP50049558A patent/JPS50149259A/ja active Pending
-
1980
- 1980-06-03 JP JP1980077269U patent/JPS5749468Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS50149259A (cs) | 1975-11-29 |
| JPS55173641U (cs) | 1980-12-12 |
| DE2420106A1 (de) | 1975-11-13 |