JPS5741053A - Terminal controlling method - Google Patents

Terminal controlling method

Info

Publication number
JPS5741053A
JPS5741053A JP55116256A JP11625680A JPS5741053A JP S5741053 A JPS5741053 A JP S5741053A JP 55116256 A JP55116256 A JP 55116256A JP 11625680 A JP11625680 A JP 11625680A JP S5741053 A JPS5741053 A JP S5741053A
Authority
JP
Japan
Prior art keywords
central processor
terminal
processor
information
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55116256A
Other languages
Japanese (ja)
Inventor
Koji Kobayashi
Kiyoshi Masuda
Kazuhiko Saka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP55116256A priority Critical patent/JPS5741053A/en
Publication of JPS5741053A publication Critical patent/JPS5741053A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To realize a common utilization of a central processor by plural slave stations, by a simple means, by sending to each slave station from the central processor a command indicating that its processor can be used. CONSTITUTION:To a control processor 50, plural terminals (slave stations) are connected in a multidrop form. In a memory 61 in the central processor 50, a memory area consisting of a timer area M1 and an area M2 for controlling each terminal equipment, etc. is provided so that one terminal does not occupy the central processor exceeding a prescribed time (for intance, 30min). In this way, a CPU60 in the central processor sends out to each terminal the information that the central processor is idle, through a series-parallel converter 63, and when a processing request is received from one specified terminal, the information that the processing is impossible is sent out to other terminals than said terminal.
JP55116256A 1980-08-22 1980-08-22 Terminal controlling method Pending JPS5741053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55116256A JPS5741053A (en) 1980-08-22 1980-08-22 Terminal controlling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55116256A JPS5741053A (en) 1980-08-22 1980-08-22 Terminal controlling method

Publications (1)

Publication Number Publication Date
JPS5741053A true JPS5741053A (en) 1982-03-06

Family

ID=14682604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55116256A Pending JPS5741053A (en) 1980-08-22 1980-08-22 Terminal controlling method

Country Status (1)

Country Link
JP (1) JPS5741053A (en)

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