JPS5734233A - Exclusive control for data output system - Google Patents

Exclusive control for data output system

Info

Publication number
JPS5734233A
JPS5734233A JP10847780A JP10847780A JPS5734233A JP S5734233 A JPS5734233 A JP S5734233A JP 10847780 A JP10847780 A JP 10847780A JP 10847780 A JP10847780 A JP 10847780A JP S5734233 A JPS5734233 A JP S5734233A
Authority
JP
Japan
Prior art keywords
fep
sends
reception
host computers
printer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10847780A
Other languages
Japanese (ja)
Inventor
Yoji Takahashi
Shigeru Wada
Morikazu Noaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10847780A priority Critical patent/JPS5734233A/en
Publication of JPS5734233A publication Critical patent/JPS5734233A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To prevent messages outputted from plural host computers from mutual interference by installing a front end processor FEP between the plural host computers and a common terminal. CONSTITUTION:A front end processor FEP is installed between plural host computers HC1 and HC2 and a common terminal controller TC. The TC controls a display DISP and a printer PR. When the host computer HC1 generates a transmission request to communicate with the printer PR, the FEP receives the request and, after checking that the other computer is not being in communication with the PR, sends a signal of reception OK to the HC1. When receiving the signal of reception OK, the HC1 sends the 1st block of a message to the PR. The PR prints out the received 1st block and, after finishing the printing, sends output completion information to the HC1. From the point of time, the FEP starts monitoring for a longer time than the time interval in blocking the message. When receiving a transmission request from the host computer HC2 during the monitoring, the FEP sends back reception disable NG to the HC2, preventing the mutual interference of messages outputted from HC1 and HC2.
JP10847780A 1980-08-07 1980-08-07 Exclusive control for data output system Pending JPS5734233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10847780A JPS5734233A (en) 1980-08-07 1980-08-07 Exclusive control for data output system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10847780A JPS5734233A (en) 1980-08-07 1980-08-07 Exclusive control for data output system

Publications (1)

Publication Number Publication Date
JPS5734233A true JPS5734233A (en) 1982-02-24

Family

ID=14485741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10847780A Pending JPS5734233A (en) 1980-08-07 1980-08-07 Exclusive control for data output system

Country Status (1)

Country Link
JP (1) JPS5734233A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0442813A (en) * 1990-06-07 1992-02-13 Nippon Kenmazai Kogyo Kk Molten zirconia fireproofing material having high-temperature heat resistance and corrosion resistance and its production
US5694619A (en) * 1993-09-20 1997-12-02 Fujitsu Limited System for exclusively controlling access of a semiconductor memory module using a backup memory and compression and decompression techniques

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0442813A (en) * 1990-06-07 1992-02-13 Nippon Kenmazai Kogyo Kk Molten zirconia fireproofing material having high-temperature heat resistance and corrosion resistance and its production
US5694619A (en) * 1993-09-20 1997-12-02 Fujitsu Limited System for exclusively controlling access of a semiconductor memory module using a backup memory and compression and decompression techniques
US5925111A (en) * 1993-09-20 1999-07-20 Fujitsu, Limited System for alotting logical path number to logical interfaces and permitting logical interface to access selected I/O using logical path number when selected I/O is not in use
US6338101B1 (en) 1993-09-20 2002-01-08 Fujitsu Limited Memory initialization method for volatile memory

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