JPS5733856A - Circuit quality monitoring circuit - Google Patents

Circuit quality monitoring circuit

Info

Publication number
JPS5733856A
JPS5733856A JP10817580A JP10817580A JPS5733856A JP S5733856 A JPS5733856 A JP S5733856A JP 10817580 A JP10817580 A JP 10817580A JP 10817580 A JP10817580 A JP 10817580A JP S5733856 A JPS5733856 A JP S5733856A
Authority
JP
Japan
Prior art keywords
circuit
waveform
shows
quality monitoring
lamp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10817580A
Other languages
Japanese (ja)
Inventor
Shizuo Sugiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP10817580A priority Critical patent/JPS5733856A/en
Publication of JPS5733856A publication Critical patent/JPS5733856A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/20Arrangements for detecting or preventing errors in the information received using signal quality detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Dc Digital Transmission (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE:To automatically confirm a transmission performance of a circuit, by adding a simple circuit, and displaying a state of an eye pattern by a light emission diode. CONSTITUTION:The side I shows a normal state in which the transmission circuit has a good quality, and the side I shows its deteriorated state. A waveform (a) shows a waveform of an eye pattern output signal and a waveform (b) shows an absolute value of the waveform (a), respectively. The waveform (b) is A/D-converted, and is digitally displayed as (c) by 5 digits of A0 to A5. This digital value is stored in an FF, etc., a lamp is driven by an output signal of the FF, and it is displayed by the lamp as shown in (f). By this display, whether a transmission performance of the circuit is good or not is decided.
JP10817580A 1980-08-08 1980-08-08 Circuit quality monitoring circuit Pending JPS5733856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10817580A JPS5733856A (en) 1980-08-08 1980-08-08 Circuit quality monitoring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10817580A JPS5733856A (en) 1980-08-08 1980-08-08 Circuit quality monitoring circuit

Publications (1)

Publication Number Publication Date
JPS5733856A true JPS5733856A (en) 1982-02-24

Family

ID=14477882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10817580A Pending JPS5733856A (en) 1980-08-08 1980-08-08 Circuit quality monitoring circuit

Country Status (1)

Country Link
JP (1) JPS5733856A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62172841A (en) * 1986-01-27 1987-07-29 Hitachi Ltd Receiving fault detecting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62172841A (en) * 1986-01-27 1987-07-29 Hitachi Ltd Receiving fault detecting system

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