JPS5731043A - Semiconductor operating circuit - Google Patents

Semiconductor operating circuit

Info

Publication number
JPS5731043A
JPS5731043A JP10575080A JP10575080A JPS5731043A JP S5731043 A JPS5731043 A JP S5731043A JP 10575080 A JP10575080 A JP 10575080A JP 10575080 A JP10575080 A JP 10575080A JP S5731043 A JPS5731043 A JP S5731043A
Authority
JP
Japan
Prior art keywords
mos
circuits
latching circuit
constituted
power consumption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10575080A
Other languages
Japanese (ja)
Inventor
Akiyoshi Kanuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10575080A priority Critical patent/JPS5731043A/en
Publication of JPS5731043A publication Critical patent/JPS5731043A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To reduce a chip area and power consumption, by effectively utilizing a parasitic capacity being incidental to an MOS transistor, and simplifying a latching circuit, in a semiconductor operating circuit of an MOS type, for executing a pipeline operation processing. CONSTITUTION:A latching circuit 2 is constituted of inverting circuits 21, 22 consisting of MOS transistors which have been cascaded in two stages, and transfer gates 23, 24 of MOS structure, which are provided on each input terminal of said circuits and are driven by clocks phi1, phi2. Since the circuits 21, 22 of each stage containing said each gate 23, 24 are constituted of an MOS transistor TR, respectively, between this transistor and the substrate exist parasitic capacities 25, 26. The latch operation is executed by positively utilizing these capacities 25, 26. In this way, the latching circuit is simplified, a propagation delay time is shortened, and also a chip area and power consumption are reduced.
JP10575080A 1980-07-31 1980-07-31 Semiconductor operating circuit Pending JPS5731043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10575080A JPS5731043A (en) 1980-07-31 1980-07-31 Semiconductor operating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10575080A JPS5731043A (en) 1980-07-31 1980-07-31 Semiconductor operating circuit

Publications (1)

Publication Number Publication Date
JPS5731043A true JPS5731043A (en) 1982-02-19

Family

ID=14415916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10575080A Pending JPS5731043A (en) 1980-07-31 1980-07-31 Semiconductor operating circuit

Country Status (1)

Country Link
JP (1) JPS5731043A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61192116U (en) * 1985-05-17 1986-11-29
JPS6337741A (en) * 1986-07-28 1988-02-18 テクトロニックス・インコ−ポレイテッド Digital heterodyne circuit
JPH01189724A (en) * 1988-01-25 1989-07-28 Oki Electric Ind Co Ltd Parallel multiplier
JPH0695853A (en) * 1992-04-10 1994-04-08 Sgs Thomson Microelettronica Spa Diagonal-propagating digital multiplier
US6744294B1 (en) 1999-05-12 2004-06-01 Telefonaktiebolaget Lm Ericsson (Publ) Cascode signal driver with low harmonic content

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61192116U (en) * 1985-05-17 1986-11-29
JPH0249447Y2 (en) * 1985-05-17 1990-12-26
JPS6337741A (en) * 1986-07-28 1988-02-18 テクトロニックス・インコ−ポレイテッド Digital heterodyne circuit
JPH01189724A (en) * 1988-01-25 1989-07-28 Oki Electric Ind Co Ltd Parallel multiplier
JPH0695853A (en) * 1992-04-10 1994-04-08 Sgs Thomson Microelettronica Spa Diagonal-propagating digital multiplier
US6744294B1 (en) 1999-05-12 2004-06-01 Telefonaktiebolaget Lm Ericsson (Publ) Cascode signal driver with low harmonic content
US7205807B2 (en) 1999-05-12 2007-04-17 Telefonaktiebolaget L M Ericsson (Publ) Cascode signal driver with low harmonic content

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