JPS5730175A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5730175A
JPS5730175A JP10459680A JP10459680A JPS5730175A JP S5730175 A JPS5730175 A JP S5730175A JP 10459680 A JP10459680 A JP 10459680A JP 10459680 A JP10459680 A JP 10459680A JP S5730175 A JPS5730175 A JP S5730175A
Authority
JP
Japan
Prior art keywords
transferred
value
address
segment
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10459680A
Other languages
Japanese (ja)
Inventor
Hideyasu Fukazawa
Akira Nonogaki
Tetsuo Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10459680A priority Critical patent/JPS5730175A/en
Publication of JPS5730175A publication Critical patent/JPS5730175A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To save a time for address calculation or the number of hardwares by adding an absolute base address in a segment and a displacement value for accessing. CONSTITUTION:While bits of an absolute base address A0 in a segment are transferred to an adder 6, a value D from the displacement part 4-2 of an address assignment part 4 under instruction is also transferred to the adder 6, which adds the value D and the bits of the address A0 together. The resulting sum is transferred to a comparator 9. To this comparator 9, the upper limit value of the segment is transferred from a limit register 3, and when the sum is greater than the upper limit value, an access error is reported.
JP10459680A 1980-07-30 1980-07-30 Information processor Pending JPS5730175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10459680A JPS5730175A (en) 1980-07-30 1980-07-30 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10459680A JPS5730175A (en) 1980-07-30 1980-07-30 Information processor

Publications (1)

Publication Number Publication Date
JPS5730175A true JPS5730175A (en) 1982-02-18

Family

ID=14384801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10459680A Pending JPS5730175A (en) 1980-07-30 1980-07-30 Information processor

Country Status (1)

Country Link
JP (1) JPS5730175A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008027236A (en) * 2006-07-21 2008-02-07 Mitsubishi Electric Corp Programmable controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008027236A (en) * 2006-07-21 2008-02-07 Mitsubishi Electric Corp Programmable controller
JP4588671B2 (en) * 2006-07-21 2010-12-01 三菱電機株式会社 Programmable controller

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