JPS5729849B2 - - Google Patents
Info
- Publication number
- JPS5729849B2 JPS5729849B2 JP8934072A JP8934072A JPS5729849B2 JP S5729849 B2 JPS5729849 B2 JP S5729849B2 JP 8934072 A JP8934072 A JP 8934072A JP 8934072 A JP8934072 A JP 8934072A JP S5729849 B2 JPS5729849 B2 JP S5729849B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8934072A JPS5729849B2 (enExample) | 1972-09-05 | 1972-09-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8934072A JPS5729849B2 (enExample) | 1972-09-05 | 1972-09-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4946378A JPS4946378A (enExample) | 1974-05-02 |
| JPS5729849B2 true JPS5729849B2 (enExample) | 1982-06-25 |
Family
ID=13967950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8934072A Expired JPS5729849B2 (enExample) | 1972-09-05 | 1972-09-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5729849B2 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5950512B2 (ja) * | 1974-12-24 | 1984-12-08 | 三菱樹脂株式会社 | 不銹鋼外観を有するプラスチツク積層金属板 |
| JPS5250385A (en) * | 1975-10-20 | 1977-04-22 | Yoshihito Tsumura | Process for producing coated metal plaes |
| JPS56110660U (enExample) * | 1980-12-23 | 1981-08-27 | ||
| JPS59193039A (ja) * | 1983-04-15 | 1984-11-01 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
| JP2748620B2 (ja) * | 1989-12-01 | 1998-05-13 | 富士通株式会社 | 半導体装置 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4854869A (enExample) * | 1971-11-09 | 1973-08-01 |
-
1972
- 1972-09-05 JP JP8934072A patent/JPS5729849B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS4946378A (enExample) | 1974-05-02 |