JPS5724146A - Loop constituting system for control information line - Google Patents

Loop constituting system for control information line

Info

Publication number
JPS5724146A
JPS5724146A JP9871580A JP9871580A JPS5724146A JP S5724146 A JPS5724146 A JP S5724146A JP 9871580 A JP9871580 A JP 9871580A JP 9871580 A JP9871580 A JP 9871580A JP S5724146 A JPS5724146 A JP S5724146A
Authority
JP
Japan
Prior art keywords
control information
exchange control
time
written
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9871580A
Other languages
English (en)
Other versions
JPS5925541B2 (ja
Inventor
Mitsuo Kuramochi
Teruo Uchida
Bunichi Sato
Toshiyuki Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55098715A priority Critical patent/JPS5925541B2/ja
Publication of JPS5724146A publication Critical patent/JPS5724146A/ja
Publication of JPS5925541B2 publication Critical patent/JPS5925541B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Exchange Systems With Centralized Control (AREA)
JP55098715A 1980-07-21 1980-07-21 制御情報線のル−プ構成方式 Expired JPS5925541B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55098715A JPS5925541B2 (ja) 1980-07-21 1980-07-21 制御情報線のル−プ構成方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55098715A JPS5925541B2 (ja) 1980-07-21 1980-07-21 制御情報線のル−プ構成方式

Publications (2)

Publication Number Publication Date
JPS5724146A true JPS5724146A (en) 1982-02-08
JPS5925541B2 JPS5925541B2 (ja) 1984-06-19

Family

ID=14227209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55098715A Expired JPS5925541B2 (ja) 1980-07-21 1980-07-21 制御情報線のル−プ構成方式

Country Status (1)

Country Link
JP (1) JPS5925541B2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61135340U (ja) * 1985-02-14 1986-08-23

Also Published As

Publication number Publication date
JPS5925541B2 (ja) 1984-06-19

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