JPS5723174A - Arithmetic system using mask register - Google Patents

Arithmetic system using mask register

Info

Publication number
JPS5723174A
JPS5723174A JP9773480A JP9773480A JPS5723174A JP S5723174 A JPS5723174 A JP S5723174A JP 9773480 A JP9773480 A JP 9773480A JP 9773480 A JP9773480 A JP 9773480A JP S5723174 A JPS5723174 A JP S5723174A
Authority
JP
Japan
Prior art keywords
vector
arithmetic
register
mask
mask register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9773480A
Other languages
Japanese (ja)
Other versions
JPS6053908B2 (en
Inventor
Masanori Mogi
Keiichiro Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9773480A priority Critical patent/JPS6053908B2/en
Publication of JPS5723174A publication Critical patent/JPS5723174A/en
Publication of JPS6053908B2 publication Critical patent/JPS6053908B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To facilitate control when conditioned arithmetic is performed by performing masked vector arithmetic operations simultaneously by providing mask registers. CONSTITUTION:A vector register 2 sets many data 1 required for vector arithmetic or arithmetic results. A mask register part 3 sets mask bits to be used for the vector arithmetic. Both the 1st-4th operators 4-7 read data required for arithmeitc from the vector register sections of the vector register 2 to set the arithmetic results in the specified vector register sections of the vector register 2, and are controlled according to the mask bits read out from the mask register of the mask register part 3 at need or set arithmetic results in the mask register part 3.
JP9773480A 1980-07-17 1980-07-17 Arithmetic method using mask register Expired JPS6053908B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9773480A JPS6053908B2 (en) 1980-07-17 1980-07-17 Arithmetic method using mask register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9773480A JPS6053908B2 (en) 1980-07-17 1980-07-17 Arithmetic method using mask register

Publications (2)

Publication Number Publication Date
JPS5723174A true JPS5723174A (en) 1982-02-06
JPS6053908B2 JPS6053908B2 (en) 1985-11-27

Family

ID=14200116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9773480A Expired JPS6053908B2 (en) 1980-07-17 1980-07-17 Arithmetic method using mask register

Country Status (1)

Country Link
JP (1) JPS6053908B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958580A (en) * 1982-09-29 1984-04-04 Hitachi Ltd Masked vector arithmetic processor
JPS59208672A (en) * 1983-05-13 1984-11-27 Nec Corp Vector processor
EP0140299A2 (en) * 1983-10-20 1985-05-08 Nec Corporation Vector mask control system
JPS6327975A (en) * 1986-07-22 1988-02-05 Hitachi Ltd Vector arithmetic control system
JPH01284970A (en) * 1988-05-11 1989-11-16 Nec Corp Iteration arithmetic circuit
JPH01284969A (en) * 1988-05-11 1989-11-16 Nec Corp Iteration arithmetic circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958580A (en) * 1982-09-29 1984-04-04 Hitachi Ltd Masked vector arithmetic processor
JPS59208672A (en) * 1983-05-13 1984-11-27 Nec Corp Vector processor
EP0140299A2 (en) * 1983-10-20 1985-05-08 Nec Corporation Vector mask control system
JPS6327975A (en) * 1986-07-22 1988-02-05 Hitachi Ltd Vector arithmetic control system
JPH0517589B2 (en) * 1986-07-22 1993-03-09 Hitachi Ltd
JPH01284970A (en) * 1988-05-11 1989-11-16 Nec Corp Iteration arithmetic circuit
JPH01284969A (en) * 1988-05-11 1989-11-16 Nec Corp Iteration arithmetic circuit

Also Published As

Publication number Publication date
JPS6053908B2 (en) 1985-11-27

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