JPS5721731B2 - - Google Patents
Info
- Publication number
- JPS5721731B2 JPS5721731B2 JP15719676A JP15719676A JPS5721731B2 JP S5721731 B2 JPS5721731 B2 JP S5721731B2 JP 15719676 A JP15719676 A JP 15719676A JP 15719676 A JP15719676 A JP 15719676A JP S5721731 B2 JPS5721731 B2 JP S5721731B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15719676A JPS5380928A (en) | 1976-12-25 | 1976-12-25 | Renewal system for memory address |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15719676A JPS5380928A (en) | 1976-12-25 | 1976-12-25 | Renewal system for memory address |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5380928A JPS5380928A (en) | 1978-07-17 |
JPS5721731B2 true JPS5721731B2 (it) | 1982-05-10 |
Family
ID=15644291
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15719676A Granted JPS5380928A (en) | 1976-12-25 | 1976-12-25 | Renewal system for memory address |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5380928A (it) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5455133A (en) * | 1977-10-12 | 1979-05-02 | Toshiba Corp | Input-output control system |
JPS62174842A (ja) * | 1986-01-29 | 1987-07-31 | Hitachi Ltd | デ−タ処理装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5132250A (it) * | 1974-09-13 | 1976-03-18 | Hitachi Ltd | |
JPS5161747A (ja) * | 1974-11-27 | 1976-05-28 | Hitachi Ltd | Deetatensoseigyosochi |
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1976
- 1976-12-25 JP JP15719676A patent/JPS5380928A/ja active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5132250A (it) * | 1974-09-13 | 1976-03-18 | Hitachi Ltd | |
JPS5161747A (ja) * | 1974-11-27 | 1976-05-28 | Hitachi Ltd | Deetatensoseigyosochi |
Also Published As
Publication number | Publication date |
---|---|
JPS5380928A (en) | 1978-07-17 |