JPS5721182A - Voice multiplex reception circuit - Google Patents
Voice multiplex reception circuitInfo
- Publication number
- JPS5721182A JPS5721182A JP9499280A JP9499280A JPS5721182A JP S5721182 A JPS5721182 A JP S5721182A JP 9499280 A JP9499280 A JP 9499280A JP 9499280 A JP9499280 A JP 9499280A JP S5721182 A JPS5721182 A JP S5721182A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- given
- voice multiplex
- channel signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/60—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals
- H04N5/607—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals for more than one sound signal, e.g. stereo, multilanguages
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Receiver Circuits (AREA)
Abstract
PURPOSE:To prevent the malfunction for identification of voice multiplex signal due to bass tone, by detecting the presence of a control channel signal within vertical blanking period and controlling the switching control signal to a matrix circuit, in a TV voice multiplex reception circuit of intercarrier system. CONSTITUTION:An voice multiplex signal S0 consisting of a main channel signal S1, sub-channel signal S2 and control channel signal S4 is inputted to an LPF21 and BPF22. The signal S1 is given to a matrix circuit 40 from the LPF21. On the other hand, the signal S2 is detected 23 from the BPF22 and given to the circuit 40 and the signal S4 is amplified and detected and added to a detection circuit 10. A gate circuit 11 picks up the vertical blanking period of the control channel signal only and gives it to a level detection circuit 12, where frequency detection and level detection are made for high potential signal and given to the circuit 40 if the output signal exceeds a given level in the circuit 12, and if the output signal is less than the level, a low potential signal respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9499280A JPS5721182A (en) | 1980-07-14 | 1980-07-14 | Voice multiplex reception circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9499280A JPS5721182A (en) | 1980-07-14 | 1980-07-14 | Voice multiplex reception circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5721182A true JPS5721182A (en) | 1982-02-03 |
JPS6129190B2 JPS6129190B2 (en) | 1986-07-04 |
Family
ID=14125366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9499280A Granted JPS5721182A (en) | 1980-07-14 | 1980-07-14 | Voice multiplex reception circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5721182A (en) |
-
1980
- 1980-07-14 JP JP9499280A patent/JPS5721182A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6129190B2 (en) | 1986-07-04 |
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