JPS57210722A - Digital phase shifting circuit - Google Patents

Digital phase shifting circuit

Info

Publication number
JPS57210722A
JPS57210722A JP9519581A JP9519581A JPS57210722A JP S57210722 A JPS57210722 A JP S57210722A JP 9519581 A JP9519581 A JP 9519581A JP 9519581 A JP9519581 A JP 9519581A JP S57210722 A JPS57210722 A JP S57210722A
Authority
JP
Japan
Prior art keywords
output
ffs
phase
shifting circuit
phase shifting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9519581A
Other languages
Japanese (ja)
Inventor
Yasuhito Isoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9519581A priority Critical patent/JPS57210722A/en
Publication of JPS57210722A publication Critical patent/JPS57210722A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To always keep the relation of phase of two outputs constant, by providing an AND gate and a D type FF inputting an output of both FFs and a clock signal, in a phase shifting circuit in which outputs of the two FFs have phase difference of 90 deg.. CONSTITUTION:An input signal (a) is applied to an FF1 and also an FF2 via an inverting circuit 3. The output of the FFs 1 and 2 is changed at the leading of an input clock and a D-FF4 inputs the output of the FFs 1 and 2, an output of an AND gate 5 to which an input clock is inputted and the output of the circuit 3 and is operated at the rise of the clock and resets the FFs 1 and 2. The reset can be made by using a monostable multivibrator in place of the D-FF4. Thus, even if a phase shifting circuit is operated in the phase relation in error at the application of power supply, the reset is made to a desired phase relation at all times, allowing to keep the phase relation of the output at terminals (b) and (c) always constant.
JP9519581A 1981-06-22 1981-06-22 Digital phase shifting circuit Pending JPS57210722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9519581A JPS57210722A (en) 1981-06-22 1981-06-22 Digital phase shifting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9519581A JPS57210722A (en) 1981-06-22 1981-06-22 Digital phase shifting circuit

Publications (1)

Publication Number Publication Date
JPS57210722A true JPS57210722A (en) 1982-12-24

Family

ID=14130964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9519581A Pending JPS57210722A (en) 1981-06-22 1981-06-22 Digital phase shifting circuit

Country Status (1)

Country Link
JP (1) JPS57210722A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255120A (en) * 1985-05-08 1986-11-12 Nec Corp Phase adjusting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255120A (en) * 1985-05-08 1986-11-12 Nec Corp Phase adjusting circuit

Similar Documents

Publication Publication Date Title
DK374875A (en) PROCEDURE FOR THE PRODUCTION OF COLOR STRONG, EASY DISPERGABLE AND FLOCKULATION STABLE COPPER PHTHALOCYANINE PIGMENTS IN THE BETA MODIFICATION AND THE USE OF THESE PIGMENTS
HK125896A (en) Digital signal coding
JPS57210722A (en) Digital phase shifting circuit
JPS5614727A (en) Phase comparator of digital pll circuit
Virsan Necessary conditions for optimal control problems with inequality-type mixed constraints(Necessary conditions for inequality-type mixed constraint optimal control, using abstract multiplier rule for Banach space of continuous and bounded measurable functions)
JPS531423A (en) Input control unit for electronic computers
JPS55108006A (en) Numeral control system
IAKUBOVICH Solution of an optimal control problem for a digital linear system
JPS5567261A (en) Synchronizing clock generation circuit
Itoh et al. 2p-M-5 TIME OF FLIGHT OF EXCITONIC POLARITONS IN CdSe
SU1193811A1 (en) Angle-to-digital converter
SU547967A1 (en) Functional code converter in voltage
JPS57201936A (en) Integrated logical circuit
JPS533149A (en) Electronic desk-top calculator
JPS5537042A (en) Remote control system
JPS52146155A (en) Phase difference generation system
JPS54157050A (en) Difference operation circuit
JPS5697142A (en) Electronic computer
Polichka et al. New Lp estimates for difference parabolic problems
種茂彰一 et al. 28p-MB-11 Reactice-n, γCrrelations in the Reactions of^< 14> N+^< 93> Nb at E_< lab.>= 210 Mev
GERANIN et al. Rounding noise in M-stage recursive digital filter(Abstract Only)
JPS54159140A (en) Error correction circuit
JPS52123827A (en) Phase shifting circuit
JPS5657175A (en) Picture processing system
JPS5426634A (en) Electronic desk calculator with function of solution of quadratioc equation