JPS57209560A - Failure detecting method for composite computer system - Google Patents
Failure detecting method for composite computer systemInfo
- Publication number
- JPS57209560A JPS57209560A JP56094862A JP9486281A JPS57209560A JP S57209560 A JPS57209560 A JP S57209560A JP 56094862 A JP56094862 A JP 56094862A JP 9486281 A JP9486281 A JP 9486281A JP S57209560 A JPS57209560 A JP S57209560A
- Authority
- JP
- Japan
- Prior art keywords
- computer
- check signal
- statistics
- computers
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
Abstract
PURPOSE:To perform failure detection, by assuming a computer out of a composite computer as a master computer, transmitting a check signal periodically from this computer to the other computers, and discriminating the presence/ absence of the abnormity of a response time from a statistics assuming the response time of each computer as a function of an elapsed time. CONSTITUTION:One computer out of a plurality of computers constituting a composite computer system is taken as a master computer and a check signal is transmitted to each computer from this master computer at each prescribed period. The computer receiving this check signal transmits a response signal to the master computer. It is determined that the operation to detect the check signal and to transmit the response signal is not performed to other processing operations with priority. T(t,i) at various points of time is measured as to all the computers, the statistics at the normal operation as to each computer is made in advance, and whether or not the response time newly measured is discriminated from the said statistics.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56094862A JPS57209560A (en) | 1981-06-19 | 1981-06-19 | Failure detecting method for composite computer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56094862A JPS57209560A (en) | 1981-06-19 | 1981-06-19 | Failure detecting method for composite computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57209560A true JPS57209560A (en) | 1982-12-22 |
Family
ID=14121838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56094862A Pending JPS57209560A (en) | 1981-06-19 | 1981-06-19 | Failure detecting method for composite computer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57209560A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62135950A (en) * | 1985-12-09 | 1987-06-18 | Fujitsu Ltd | Fault state informing system |
-
1981
- 1981-06-19 JP JP56094862A patent/JPS57209560A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62135950A (en) * | 1985-12-09 | 1987-06-18 | Fujitsu Ltd | Fault state informing system |
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