JPS57209554A - Data processor - Google Patents

Data processor

Info

Publication number
JPS57209554A
JPS57209554A JP9402081A JP9402081A JPS57209554A JP S57209554 A JPS57209554 A JP S57209554A JP 9402081 A JP9402081 A JP 9402081A JP 9402081 A JP9402081 A JP 9402081A JP S57209554 A JPS57209554 A JP S57209554A
Authority
JP
Japan
Prior art keywords
data
storage device
transfer path
cpu
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9402081A
Other languages
Japanese (ja)
Inventor
Takashi Watanabe
Koichi Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP9402081A priority Critical patent/JPS57209554A/en
Publication of JPS57209554A publication Critical patent/JPS57209554A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To perform data transfer between a CPU and a storage device smoothly in a high speed, by providing a data editing device to a data transfer path connecting the CPU and the storage device. CONSTITUTION:A data transfer path 3 connecting a CPU 1 and a storage device 2 is provided with a data switch circuit 6 which exchanges the position of data on the transfer path in byte unit and a stack register 5 having a capacity larger than the width of data of the data transfer path 3 connected in the CPU 1. Further, data are read out from a stack register 5 at an operation circuit 4 with an address register 7 representing the data storage address in the storage device 2 and a count register 8 designating the number of transfer data, the conversion in byte unit on the data transfer path 3 is made and the data are transferred to the storage device 2. The data transferred from the storage device 2 are converted in byte unit and written in the stack register 5.
JP9402081A 1981-06-19 1981-06-19 Data processor Pending JPS57209554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9402081A JPS57209554A (en) 1981-06-19 1981-06-19 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9402081A JPS57209554A (en) 1981-06-19 1981-06-19 Data processor

Publications (1)

Publication Number Publication Date
JPS57209554A true JPS57209554A (en) 1982-12-22

Family

ID=14098855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9402081A Pending JPS57209554A (en) 1981-06-19 1981-06-19 Data processor

Country Status (1)

Country Link
JP (1) JPS57209554A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6428752A (en) * 1987-07-24 1989-01-31 Toshiba Corp Data processor
JPH03505016A (en) * 1989-03-15 1991-10-31 エイエスティー・リサーチ，インコーポレイテッド Controller for direct memory access
JPH04125745A (en) * 1990-09-18 1992-04-27 Fujitsu Ltd Method and device for data write control
JPH04148424A (en) * 1990-10-12 1992-05-21 Nec Corp Logical simulation operation circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6428752A (en) * 1987-07-24 1989-01-31 Toshiba Corp Data processor
JPH03505016A (en) * 1989-03-15 1991-10-31 エイエスティー・リサーチ，インコーポレイテッド Controller for direct memory access
JPH04125745A (en) * 1990-09-18 1992-04-27 Fujitsu Ltd Method and device for data write control
JPH04148424A (en) * 1990-10-12 1992-05-21 Nec Corp Logical simulation operation circuit

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