JPS57208706A - Audio muting circuit - Google Patents

Audio muting circuit

Info

Publication number
JPS57208706A
JPS57208706A JP56094795A JP9479581A JPS57208706A JP S57208706 A JPS57208706 A JP S57208706A JP 56094795 A JP56094795 A JP 56094795A JP 9479581 A JP9479581 A JP 9479581A JP S57208706 A JPS57208706 A JP S57208706A
Authority
JP
Japan
Prior art keywords
circuit
audio
driving
trs
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56094795A
Other languages
Japanese (ja)
Inventor
Nobuhiro Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP56094795A priority Critical patent/JPS57208706A/en
Publication of JPS57208706A publication Critical patent/JPS57208706A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE: To attain circuit integration in high speed without noise, by constituting the titled circuit with a variable attenuation circuit, its driving circuit and an audio clock generating circuit.
CONSTITUTION: A variable attenuation circuit R consists of a plurality of series- connected resistors R1, R2 and R3, and switching transistors(TR) T1, T2 and T3 between each connecting point of each resistor and ground. A driving circuit D driving the TRs T1∼T3 comprises a flip-flop circuit DF inputting a clock C from an audio clock generating circuit and taking a mute signal IM provided in the form of a unit function as a D input, and the 1st and 2nd flip-flops TF1 and TF2 constituting a counter counting the audio clock inputted to a terminal T only when a reset pulse is given to a reset terminal, and at the muting, the TRs are sequentially conducted from the TR at ground side in synchronizing with the zero cross point of the audio signal transmitted from the audio channel.
COPYRIGHT: (C)1982,JPO&Japio
JP56094795A 1981-06-18 1981-06-18 Audio muting circuit Pending JPS57208706A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56094795A JPS57208706A (en) 1981-06-18 1981-06-18 Audio muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56094795A JPS57208706A (en) 1981-06-18 1981-06-18 Audio muting circuit

Publications (1)

Publication Number Publication Date
JPS57208706A true JPS57208706A (en) 1982-12-21

Family

ID=14120001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56094795A Pending JPS57208706A (en) 1981-06-18 1981-06-18 Audio muting circuit

Country Status (1)

Country Link
JP (1) JPS57208706A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS544047A (en) * 1977-06-13 1979-01-12 Victor Co Of Japan Ltd Switching circuit
JPS5532216A (en) * 1978-08-23 1980-03-06 Matsushita Electric Ind Co Ltd Automatic recording level setter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS544047A (en) * 1977-06-13 1979-01-12 Victor Co Of Japan Ltd Switching circuit
JPS5532216A (en) * 1978-08-23 1980-03-06 Matsushita Electric Ind Co Ltd Automatic recording level setter

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