JPS57203294A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS57203294A
JPS57203294A JP8899881A JP8899881A JPS57203294A JP S57203294 A JPS57203294 A JP S57203294A JP 8899881 A JP8899881 A JP 8899881A JP 8899881 A JP8899881 A JP 8899881A JP S57203294 A JPS57203294 A JP S57203294A
Authority
JP
Japan
Prior art keywords
lines
turned
input
status
pressure resisting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8899881A
Other languages
Japanese (ja)
Other versions
JPS6126160B2 (en
Inventor
Kazuyoshi Tsuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8899881A priority Critical patent/JPS57203294A/en
Publication of JPS57203294A publication Critical patent/JPS57203294A/en
Publication of JPS6126160B2 publication Critical patent/JPS6126160B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To easily detect pressure resisting defects between the collector and substrate of a memory cell by connecting diodes to the lines of a memory cell array and applying prescribed constant voltage to the lines.
CONSTITUTION: When a terminal CE is turned to a high level to make it writing status, buffers OB1, OB2 are turned off, output lines O1, O2 are turned to high impedance status, and a transistor (TR) T is turned on through an input A1/2 and a Zener diode DE2, all the lines of decoder Dx on the output side are turned to high level output status. The electric potential of an input A1/1 applying prescribed potential difference to the lines through the input A1/1, Zener diode DE2 and diodes DC1, DC2... connected to the lines by the common connection line to that of the diode DE2 is made pressure resisting voltage between the collector and substrate of a memory cell C formed by the base opening transistors of memory array cells. Thus, the pressure resisting status of all the memory cells before writing is easily detected by connecting accurate resistance to the input A1/1, applying pressure resisting voltage to an opening end and checking whether current flows into the input A1/1 or not.
COPYRIGHT: (C)1982,JPO&Japio
JP8899881A 1981-06-10 1981-06-10 Semiconductor integrated circuit Granted JPS57203294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8899881A JPS57203294A (en) 1981-06-10 1981-06-10 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8899881A JPS57203294A (en) 1981-06-10 1981-06-10 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS57203294A true JPS57203294A (en) 1982-12-13
JPS6126160B2 JPS6126160B2 (en) 1986-06-19

Family

ID=13958473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8899881A Granted JPS57203294A (en) 1981-06-10 1981-06-10 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57203294A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE41733E1 (en) * 1996-03-05 2010-09-21 Contour Semiconductor, Inc. Dual-addressed rectifier storage device
US7813157B2 (en) 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6182261U (en) * 1984-11-05 1986-05-31
JPS6442451U (en) * 1987-09-10 1989-03-14
JPH03165247A (en) * 1989-11-24 1991-07-17 Yamatake Honeywell Co Ltd Moisture sensitive device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE41733E1 (en) * 1996-03-05 2010-09-21 Contour Semiconductor, Inc. Dual-addressed rectifier storage device
USRE42310E1 (en) 1996-03-05 2011-04-26 Contour Semiconductor, Inc. Dual-addressed rectifier storage device
US7813157B2 (en) 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory

Also Published As

Publication number Publication date
JPS6126160B2 (en) 1986-06-19

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