JPS57201356A - Multiple address number informing system - Google Patents
Multiple address number informing systemInfo
- Publication number
- JPS57201356A JPS57201356A JP8500581A JP8500581A JPS57201356A JP S57201356 A JPS57201356 A JP S57201356A JP 8500581 A JP8500581 A JP 8500581A JP 8500581 A JP8500581 A JP 8500581A JP S57201356 A JPS57201356 A JP S57201356A
- Authority
- JP
- Japan
- Prior art keywords
- multiple address
- cpu8
- abbreviated
- exchange
- address number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/16—Arrangements for providing special services to substations
- H04L12/18—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
PURPOSE:To improve service of whole network and enable access to plural terminating terminals of multiple address by one touch push down of an address key by performing processing of multiple address development in an originating terminal. CONSTITUTION:A switching relay 19 is initially set beforehand so as to be able to connect with an adapter 16, and an abbreviated multiple address number is inputted by one touch push down of an address key from a key operating section 15. By this, I/O port 12 makes interruption to CPU8, and a control program contained in ROM9 operates and reads inputted abbreviated multiple address number in CPU8. CPU8 takes out plural actual adress numbers developed for multiple address corresponding to abbreviated multiple address numbers from RAM10, and stores in a temporary storage area. CPU8 instructs access of a store and forward exchange 2 to a dial sending section 11. The dial sending section 11 calls the exchange 2 and makes circuit setting. Then, multiple address number is transferred to the exchange 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8500581A JPS57201356A (en) | 1981-06-04 | 1981-06-04 | Multiple address number informing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8500581A JPS57201356A (en) | 1981-06-04 | 1981-06-04 | Multiple address number informing system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57201356A true JPS57201356A (en) | 1982-12-09 |
JPH0211060B2 JPH0211060B2 (en) | 1990-03-12 |
Family
ID=13846608
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8500581A Granted JPS57201356A (en) | 1981-06-04 | 1981-06-04 | Multiple address number informing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57201356A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52128001A (en) * | 1976-04-20 | 1977-10-27 | Nec Corp | Automatic address adding system |
JPS57148448A (en) * | 1981-03-09 | 1982-09-13 | Nippon Telegr & Teleph Corp <Ntt> | Multiple address communication terminal controller |
-
1981
- 1981-06-04 JP JP8500581A patent/JPS57201356A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52128001A (en) * | 1976-04-20 | 1977-10-27 | Nec Corp | Automatic address adding system |
JPS57148448A (en) * | 1981-03-09 | 1982-09-13 | Nippon Telegr & Teleph Corp <Ntt> | Multiple address communication terminal controller |
Also Published As
Publication number | Publication date |
---|---|
JPH0211060B2 (en) | 1990-03-12 |
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