JPS57182254A - Testing method for multicomputer controlling system - Google Patents

Testing method for multicomputer controlling system

Info

Publication number
JPS57182254A
JPS57182254A JP56064150A JP6415081A JPS57182254A JP S57182254 A JPS57182254 A JP S57182254A JP 56064150 A JP56064150 A JP 56064150A JP 6415081 A JP6415081 A JP 6415081A JP S57182254 A JPS57182254 A JP S57182254A
Authority
JP
Japan
Prior art keywords
storage device
processing
multicomputer
confirmation test
controlling system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56064150A
Other languages
Japanese (ja)
Inventor
Masahiro Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Information and Control Systems Inc
Original Assignee
Hitachi Ltd
Hitachi Control Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Control Systems Inc filed Critical Hitachi Ltd
Priority to JP56064150A priority Critical patent/JPS57182254A/en
Publication of JPS57182254A publication Critical patent/JPS57182254A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

PURPOSE:To facilitate a confirmation test during a test of a multicomputer controlling system, by varying the coordination between logical addresses and physical addresses of areas in a commonuse storage device between computers which have contention in online control processing and confirmation test processing. CONSTITUTION:A multicomputer controlling system has three computers including arithmetic devices 200-400 and an intercomputer commonuse storage device 100 of doubled structure. When an indication for the start of a confirmation test is sent from a system console 500 to a desired computer, e.g. the 3rd computer, the indication is inputted through an input and output controller 430 to the arithmetic controller 400, and by a system console processing program stored therein, the coordination between the logical and physical addresses areas in the storage device 100 having contention in online processing and confirmation test processing in an address coordination part 410 is changed into the physical address of an area secured previously in a main storage device 420, so that even when the program performs storage in the area of the storage device 100, storage in the area of the main storage device 420 is performed.
JP56064150A 1981-04-30 1981-04-30 Testing method for multicomputer controlling system Pending JPS57182254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56064150A JPS57182254A (en) 1981-04-30 1981-04-30 Testing method for multicomputer controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56064150A JPS57182254A (en) 1981-04-30 1981-04-30 Testing method for multicomputer controlling system

Publications (1)

Publication Number Publication Date
JPS57182254A true JPS57182254A (en) 1982-11-10

Family

ID=13249752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56064150A Pending JPS57182254A (en) 1981-04-30 1981-04-30 Testing method for multicomputer controlling system

Country Status (1)

Country Link
JP (1) JPS57182254A (en)

Similar Documents

Publication Publication Date Title
JPS55146552A (en) N 1 backkup method of dispersion type hierarchy system
JPS54114687A (en) Sequence controller
JPS5717019A (en) Numerical controller
EP0287295A3 (en) Multiple i/o bus virtual broadcast of programmed i/o instructions
JPS57182254A (en) Testing method for multicomputer controlling system
JPS576947A (en) Test processing system of on-line process system
JPS56153407A (en) Sequential control device
JPS5495133A (en) Input/output processing control system
JPS57201947A (en) Preventing method for interruption malfunction of computer
JPS57193807A (en) Numerical controller
JPS6433658A (en) Computer system
JPS56117259A (en) Control method of copying machine
JPS55112624A (en) Diagnosis unit for input and output bus and input and output device
JPS5674738A (en) Transfer system of display data
JPS6426256A (en) Data changing method
JPS54145447A (en) Input-output control system
JPS55138155A (en) File processing system
JPS5654517A (en) Process display method
JPS51112245A (en) Monitor control system of electronic computer organization
JPS6446845A (en) Simulation system for microcomputer
JPS647153A (en) System controller for computer
JPS55938A (en) Online monitor unit of sequnce controller
JPS55146555A (en) Simulation test device
JPS5794848A (en) Loading system of microprogram
FR2447577A1 (en) Multiple processor computer system - adopts initial interconnection structure until re-configured under program control