JPS57180288A - Mixed loading system of analog and digital trunks - Google Patents

Mixed loading system of analog and digital trunks

Info

Publication number
JPS57180288A
JPS57180288A JP6467781A JP6467781A JPS57180288A JP S57180288 A JPS57180288 A JP S57180288A JP 6467781 A JP6467781 A JP 6467781A JP 6467781 A JP6467781 A JP 6467781A JP S57180288 A JPS57180288 A JP S57180288A
Authority
JP
Japan
Prior art keywords
trunk
loading
circuit
analog
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6467781A
Other languages
Japanese (ja)
Inventor
Yoshio Sugiura
Toshihiko Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP6467781A priority Critical patent/JPS57180288A/en
Publication of JPS57180288A publication Critical patent/JPS57180288A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Structure Of Telephone Exchanges (AREA)

Abstract

PURPOSE:To make effective use of loading area, by loading a digital trunk circuit constituting a connection unit at each digital junction line to a trunk loading area, and mixedly loading analog and digital trunks to a trunk loading area. CONSTITUTION:Analog trunk packages ATRKP0-ATRKP4 are respectively constituted with a analog trunk circuit 6 consisting of a hybrid transformer HYB, a coder decoder filter circuit CODECEIL and a trunk control circuit TRC. The packages ATRKP0-ATRKP4 are assumed as an loading unit with 5 cards 30 circuits. Further, a digital trunk package group DTRK-PG0 is constituted as one circuit consisting of a terminal circuit ET and a monitor signal control circuit SSC, and this group DTRK-PG0 and one loading unit 5 are loaded to a trunk unit TRKU. Then, the transmission/reception of voice and monitor signals is executed for a trunk processor TRKPR and a time division network TDNW.
JP6467781A 1981-04-28 1981-04-28 Mixed loading system of analog and digital trunks Pending JPS57180288A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6467781A JPS57180288A (en) 1981-04-28 1981-04-28 Mixed loading system of analog and digital trunks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6467781A JPS57180288A (en) 1981-04-28 1981-04-28 Mixed loading system of analog and digital trunks

Publications (1)

Publication Number Publication Date
JPS57180288A true JPS57180288A (en) 1982-11-06

Family

ID=13265033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6467781A Pending JPS57180288A (en) 1981-04-28 1981-04-28 Mixed loading system of analog and digital trunks

Country Status (1)

Country Link
JP (1) JPS57180288A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595483A (en) * 1979-01-16 1980-07-19 Nec Corp Trunk unit system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595483A (en) * 1979-01-16 1980-07-19 Nec Corp Trunk unit system

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