JPS5717286A - Video signal recording circuit - Google Patents

Video signal recording circuit

Info

Publication number
JPS5717286A
JPS5717286A JP9064780A JP9064780A JPS5717286A JP S5717286 A JPS5717286 A JP S5717286A JP 9064780 A JP9064780 A JP 9064780A JP 9064780 A JP9064780 A JP 9064780A JP S5717286 A JPS5717286 A JP S5717286A
Authority
JP
Japan
Prior art keywords
trq
terminal
differential amplifier
video signal
monolithic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9064780A
Other languages
Japanese (ja)
Other versions
JPH027228B2 (en
Inventor
Koichi Hirose
Akira Shibata
Keiichi Komatsu
Hitoshi Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9064780A priority Critical patent/JPS5717286A/en
Publication of JPS5717286A publication Critical patent/JPS5717286A/en
Publication of JPH027228B2 publication Critical patent/JPH027228B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE: To reduce the waveform distortion due to clipping and to avoid the variance in FM allocation, by constituting a feedback loop so that the difference of temperature characteristic between elements in a monolithic IC and peripheral components can not be affected.
CONSTITUTION: Transistors (TRs) Q7, Q8 constitute a differential amplifier, a signal amplified at this differential amplifier is picked up at the collector of the TRQ8 and applied to a clip circuit 8 via a buffer TRQ9. A signal outputted from a terminal (c) is given to a terminal (j) of a monolithic IC27 via a buffer circuit 35 consisting of a TRQ6 and resistor R15, level shift circuit 36 consisting of a Zener diode D2, capacitor C6, and resistor R16, and R17, and the terminal (j) is connected to the base of the TRQ8 constituting a differential amplifier to form a negative feedback loop.
COPYRIGHT: (C)1982,JPO&Japio
JP9064780A 1980-07-04 1980-07-04 Video signal recording circuit Granted JPS5717286A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9064780A JPS5717286A (en) 1980-07-04 1980-07-04 Video signal recording circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9064780A JPS5717286A (en) 1980-07-04 1980-07-04 Video signal recording circuit

Publications (2)

Publication Number Publication Date
JPS5717286A true JPS5717286A (en) 1982-01-28
JPH027228B2 JPH027228B2 (en) 1990-02-16

Family

ID=14004295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9064780A Granted JPS5717286A (en) 1980-07-04 1980-07-04 Video signal recording circuit

Country Status (1)

Country Link
JP (1) JPS5717286A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH059832A (en) * 1991-07-02 1993-01-19 Sanko Eng:Kk High-speed warping machine

Also Published As

Publication number Publication date
JPH027228B2 (en) 1990-02-16

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