JPS57168548A - Noise eliminating device - Google Patents
Noise eliminating deviceInfo
- Publication number
- JPS57168548A JPS57168548A JP56053100A JP5310081A JPS57168548A JP S57168548 A JPS57168548 A JP S57168548A JP 56053100 A JP56053100 A JP 56053100A JP 5310081 A JP5310081 A JP 5310081A JP S57168548 A JPS57168548 A JP S57168548A
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- noise
- frequency component
- transmitting
- led5a
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Noise Elimination (AREA)
Abstract
PURPOSE:To make an information processing with high fidelity between the transmitting and receiving units, by inserting a photocoupler into a clock signal transmission line and eliminating the high frequency component of the noise induced to the transmission line. CONSTITUTION:The clock signal containing the noise is amplified by a transistor TR4 of an eliminating circuit to actuate an LED5a for emission of light. The light emitted from the LED5a is received by a phototransistor 5b and then inverted by an inverter 6 to eliminate the high frequency component of the noise for the signal. The clock signal delivered from the eliminating circuit contains the residual low frequency component, and this clock signal is supplied to both the receiving and transmitting units. This clock signal contains no shift of phase to cause no shift of synchronization between the transmitting and receiving units to ensure an information process with high fidelity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56053100A JPS57168548A (en) | 1981-04-10 | 1981-04-10 | Noise eliminating device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56053100A JPS57168548A (en) | 1981-04-10 | 1981-04-10 | Noise eliminating device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57168548A true JPS57168548A (en) | 1982-10-16 |
Family
ID=12933363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56053100A Pending JPS57168548A (en) | 1981-04-10 | 1981-04-10 | Noise eliminating device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57168548A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0438151U (en) * | 1990-07-27 | 1992-03-31 |
-
1981
- 1981-04-10 JP JP56053100A patent/JPS57168548A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0438151U (en) * | 1990-07-27 | 1992-03-31 |
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