JPS57166706A - Mixer circuit - Google Patents

Mixer circuit

Info

Publication number
JPS57166706A
JPS57166706A JP5133381A JP5133381A JPS57166706A JP S57166706 A JPS57166706 A JP S57166706A JP 5133381 A JP5133381 A JP 5133381A JP 5133381 A JP5133381 A JP 5133381A JP S57166706 A JPS57166706 A JP S57166706A
Authority
JP
Japan
Prior art keywords
fet1
gate
strip line
mixer circuit
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5133381A
Other languages
Japanese (ja)
Inventor
Masayoshi Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP5133381A priority Critical patent/JPS57166706A/en
Publication of JPS57166706A publication Critical patent/JPS57166706A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D9/00—Demodulation or transference of modulation of modulated electromagnetic waves
    • H03D9/06—Transference of modulation using distributed inductance and capacitance
    • H03D9/0658—Transference of modulation using distributed inductance and capacitance by means of semiconductor devices having more than two electrodes
    • H03D9/0675—Transference of modulation using distributed inductance and capacitance by means of semiconductor devices having more than two electrodes using field effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE:To obtain a high-gain mixer circuit which has mutually independent input matching circuits, by connecting the drain of the 2nd FET to the source or gate of the 3rd FET in the mixer circuit used for an SHF band, etc. CONSTITUTION:An FET1 is constituted by connecting the drains of an FET1a and an FET1b, and the source of an FET1c common. An input signal is supplied to the terminal 2a of a circuit and led to the gate G1 of the FET1 through a strip line 17 constituting a matching stub. A local oscillation signal is supplied to the terminal 3a and then applied to the gate G2 of the FET1 through a strip line 18 constituting a matching stub. In addition, a drain voltage Vdd is applied to the drain D3 of the FET1 through an inductance L and a strip line filter 21, and an IF signal is let out through a DC cutting capacitor C6. The sources S1 and S2 of the FET1 and its gate G3 are grounded in terms of high frequency. The gate G3 of the FET1 may be connected in common.
JP5133381A 1981-04-06 1981-04-06 Mixer circuit Pending JPS57166706A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5133381A JPS57166706A (en) 1981-04-06 1981-04-06 Mixer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5133381A JPS57166706A (en) 1981-04-06 1981-04-06 Mixer circuit

Publications (1)

Publication Number Publication Date
JPS57166706A true JPS57166706A (en) 1982-10-14

Family

ID=12883987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5133381A Pending JPS57166706A (en) 1981-04-06 1981-04-06 Mixer circuit

Country Status (1)

Country Link
JP (1) JPS57166706A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323123A (en) * 1991-12-23 1994-06-21 U.S. Philips Corporation Integrated circuit having a variable-gain amplifier
EP1292018A3 (en) * 2001-09-04 2003-07-23 Kabushiki Kaisha Toshiba Balanced FET Mixer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323123A (en) * 1991-12-23 1994-06-21 U.S. Philips Corporation Integrated circuit having a variable-gain amplifier
EP1292018A3 (en) * 2001-09-04 2003-07-23 Kabushiki Kaisha Toshiba Balanced FET Mixer

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