JPS57164485A - Buffer device for address conversion - Google Patents

Buffer device for address conversion

Info

Publication number
JPS57164485A
JPS57164485A JP56049321A JP4932181A JPS57164485A JP S57164485 A JPS57164485 A JP S57164485A JP 56049321 A JP56049321 A JP 56049321A JP 4932181 A JP4932181 A JP 4932181A JP S57164485 A JPS57164485 A JP S57164485A
Authority
JP
Japan
Prior art keywords
noneffective
address conversion
sections
address
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56049321A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0258654B2 (enExample
Inventor
Mitsushi Okabayashi
Yasuo Watabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56049321A priority Critical patent/JPS57164485A/ja
Publication of JPS57164485A publication Critical patent/JPS57164485A/ja
Publication of JPH0258654B2 publication Critical patent/JPH0258654B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56049321A 1981-04-03 1981-04-03 Buffer device for address conversion Granted JPS57164485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56049321A JPS57164485A (en) 1981-04-03 1981-04-03 Buffer device for address conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56049321A JPS57164485A (en) 1981-04-03 1981-04-03 Buffer device for address conversion

Publications (2)

Publication Number Publication Date
JPS57164485A true JPS57164485A (en) 1982-10-09
JPH0258654B2 JPH0258654B2 (enExample) 1990-12-10

Family

ID=12827701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56049321A Granted JPS57164485A (en) 1981-04-03 1981-04-03 Buffer device for address conversion

Country Status (1)

Country Link
JP (1) JPS57164485A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60132253A (ja) * 1983-11-28 1985-07-15 Nec Corp アドレス変換方式
JP2019096309A (ja) * 2017-11-22 2019-06-20 エイアールエム リミテッド メンテナンス動作の実行

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60132253A (ja) * 1983-11-28 1985-07-15 Nec Corp アドレス変換方式
JP2019096309A (ja) * 2017-11-22 2019-06-20 エイアールエム リミテッド メンテナンス動作の実行

Also Published As

Publication number Publication date
JPH0258654B2 (enExample) 1990-12-10

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