JPS57159317A - Initial set control system for system - Google Patents

Initial set control system for system

Info

Publication number
JPS57159317A
JPS57159317A JP56044844A JP4484481A JPS57159317A JP S57159317 A JPS57159317 A JP S57159317A JP 56044844 A JP56044844 A JP 56044844A JP 4484481 A JP4484481 A JP 4484481A JP S57159317 A JPS57159317 A JP S57159317A
Authority
JP
Japan
Prior art keywords
data
failure
parity error
deletion
way
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56044844A
Other languages
Japanese (ja)
Other versions
JPH0119180B2 (en
Inventor
Takashi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56044844A priority Critical patent/JPS57159317A/en
Publication of JPS57159317A publication Critical patent/JPS57159317A/en
Publication of JPH0119180B2 publication Critical patent/JPH0119180B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

PURPOSE:To prevent the generation of system down due to a fixed failure in an initial program loading, by disconnecting a failed part of the system before the initial program loading of an operating system. CONSTITUTION:If a parity error exists in tag information read out from a tag section 9-0, a parity error FF15-0 is set, and a deletion FF21-0 is set with a CHECK timing. When the FF21-0 is set, a replacement circuit 8 excludes its way from the objective of replacement. Data in a data section 10-0 are set to a fatch data register 16 and if this data includes a parity error, the FF21-0 is set. If the failure is detected in the process of system effecting processing, the failure is regarded as a fixed failuren and an operation state register 20-i corresponding to the deletion FF-i which is set, is set from a service processor. Then, a way (i) is not usable even if the CPU is set.
JP56044844A 1981-03-27 1981-03-27 Initial set control system for system Granted JPS57159317A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56044844A JPS57159317A (en) 1981-03-27 1981-03-27 Initial set control system for system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56044844A JPS57159317A (en) 1981-03-27 1981-03-27 Initial set control system for system

Publications (2)

Publication Number Publication Date
JPS57159317A true JPS57159317A (en) 1982-10-01
JPH0119180B2 JPH0119180B2 (en) 1989-04-10

Family

ID=12702777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56044844A Granted JPS57159317A (en) 1981-03-27 1981-03-27 Initial set control system for system

Country Status (1)

Country Link
JP (1) JPS57159317A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111539A (en) * 1982-12-17 1984-06-27 Fujitsu Ltd Microprogram loading system
JPS60247750A (en) * 1984-05-23 1985-12-07 Nec Corp Control system for initial system constitution

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111539A (en) * 1982-12-17 1984-06-27 Fujitsu Ltd Microprogram loading system
JPH0142008B2 (en) * 1982-12-17 1989-09-08 Fujitsu Ltd
JPS60247750A (en) * 1984-05-23 1985-12-07 Nec Corp Control system for initial system constitution

Also Published As

Publication number Publication date
JPH0119180B2 (en) 1989-04-10

Similar Documents

Publication Publication Date Title
US5528755A (en) Invalid data detection, recording and nullification
WO2021169260A1 (en) System board card power supply test method, apparatus and device, and storage medium
US9535784B2 (en) Self monitoring and self repairing ECC
US4651321A (en) Apparatus for reducing storage necessary for error correction and detection in data processing machines
ATE216098T1 (en) MULTI-PROCESSOR SYSTEM BRIDGE WITH ACCESS CONTROL
EP0403415A3 (en) System and method for detecting and diagnosing errors in a computer program
DE3650651T2 (en) Fault-tolerant data processing system
HK1011155A1 (en) On-line module replacement in a multiple module data processing system
Chatzidimitriou et al. Healthlog monitor: Errors, symptoms and reactions consolidated
EP0257952B1 (en) Apparatus for detecting and classifying errors in control words
JPS57159317A (en) Initial set control system for system
CN100392608C (en) Error notification method and apparatus for an information processing
BR9001126A (en) COMPUTER MEMORY SYSTEM, DIGITAL MEMORY SYSTEM AND PROCESS TO IMPROVE THE RELIABILITY OF A MULTIPLE LEVEL MEMORY SYSTEM
JPS57105814A (en) Error correction processing system for magnetic disc device
EP0113982B1 (en) A data processing system
JPS5447540A (en) Fault correction system for control memory
KR0154477B1 (en) Method capable of backup the log file in the full electronic switching system
JPS55162162A (en) Diagnostic system for error detecting-correcting circuit
JPS5533278A (en) Error correcting processor
JPS5693196A (en) Error detecting system of checking circuit
JPS5680896A (en) Main memory device information recovery system
JPS5542318A (en) Cash memory control system
JPH06103469B2 (en) Memory control circuit
CORLUHAN et al. On an algorithm for identifying faults in a T-diagnosable system[Interim Report]
JPS6356751A (en) Memory patrol control system