JPS57152586A - Driving method of detecting amplifying circuit - Google Patents

Driving method of detecting amplifying circuit

Info

Publication number
JPS57152586A
JPS57152586A JP56039210A JP3921081A JPS57152586A JP S57152586 A JPS57152586 A JP S57152586A JP 56039210 A JP56039210 A JP 56039210A JP 3921081 A JP3921081 A JP 3921081A JP S57152586 A JPS57152586 A JP S57152586A
Authority
JP
Japan
Prior art keywords
nodal points
clock
boosting
amplifying circuit
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56039210A
Other languages
Japanese (ja)
Inventor
Masaki Hirata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56039210A priority Critical patent/JPS57152586A/en
Publication of JPS57152586A publication Critical patent/JPS57152586A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type

Landscapes

  • Static Random-Access Memory (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To prevent the occurrence of substrate currents and to secure stable operations of the detecting amplifying circuit, by cutting off the boosting means during the period where nodal points are charged through pre-charging means. CONSTITUTION:Pre-charging means 1, 2 which charge nodal points A', B', operating means 3, 3' and 4, 4' which couple input signals for a necessary period, boosting means 7, 8 which supply voltages to the nodal points A' and B' under a capacitive coupling, and an activating means 9 which controls the flip flop operatin, are installed. It is arranged that, when such a detecting amplifying circuit is driven, the boosting means 7, 8 are cut off during the period where the nodal points A', B' are charged through the precharging means 1, 2. For example, in the circuit shown in the diagram, the voltage of the nodal points A', B' is changed by giving a pre-charging clock phi1, a transferring clock phi2, a boosting clock phi3, and an activating clock phi4 at an adequate timing.
JP56039210A 1981-03-18 1981-03-18 Driving method of detecting amplifying circuit Pending JPS57152586A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56039210A JPS57152586A (en) 1981-03-18 1981-03-18 Driving method of detecting amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56039210A JPS57152586A (en) 1981-03-18 1981-03-18 Driving method of detecting amplifying circuit

Publications (1)

Publication Number Publication Date
JPS57152586A true JPS57152586A (en) 1982-09-20

Family

ID=12546768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56039210A Pending JPS57152586A (en) 1981-03-18 1981-03-18 Driving method of detecting amplifying circuit

Country Status (1)

Country Link
JP (1) JPS57152586A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1134746A2 (en) * 2000-03-08 2001-09-19 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory
US6462999B1 (en) 2000-12-18 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having internal data read circuit excellent in noise immunity

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7009878B2 (en) 2000-03-08 2006-03-07 Kabushiki Kaisha Toshiba Data reprogramming/retrieval circuit for temporarily storing programmed/retrieved data for caching and multilevel logical functions in an EEPROM
EP1134746A3 (en) * 2000-03-08 2001-11-28 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory
EP1288964A2 (en) * 2000-03-08 2003-03-05 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory
EP1288964A3 (en) * 2000-03-08 2004-11-17 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory
US6937510B2 (en) 2000-03-08 2005-08-30 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory
EP1134746A2 (en) * 2000-03-08 2001-09-19 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory
US7379340B2 (en) 2000-03-08 2008-05-27 Kabushiki Kaisha Toshiba Sense amplifier circuit in non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node
US7567463B2 (en) 2000-03-08 2009-07-28 Kabushiki Kaisha Toshiba Sense amplifier circuit in multi-level non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node
US7639544B2 (en) 2000-03-08 2009-12-29 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory
US7859907B2 (en) 2000-03-08 2010-12-28 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory
US8144513B2 (en) 2000-03-08 2012-03-27 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory
US8472268B2 (en) 2000-03-08 2013-06-25 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory and simultaneous writing of data
US6462999B1 (en) 2000-12-18 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having internal data read circuit excellent in noise immunity

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