JPS57150187A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS57150187A
JPS57150187A JP56034242A JP3424281A JPS57150187A JP S57150187 A JPS57150187 A JP S57150187A JP 56034242 A JP56034242 A JP 56034242A JP 3424281 A JP3424281 A JP 3424281A JP S57150187 A JPS57150187 A JP S57150187A
Authority
JP
Japan
Prior art keywords
lowering
readout
resistor
current
amplification factor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56034242A
Other languages
Japanese (ja)
Inventor
Kazuhiro Toyoda
Kazuo Oami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56034242A priority Critical patent/JPS57150187A/en
Publication of JPS57150187A publication Critical patent/JPS57150187A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To suppress the lowering in readout margin of a semiconductor memory formed with a resistive load type flip-flop, by compulsively lowering a readout reference level accompanied with the lowering of a current amplification factor of a transistor (TR). CONSTITUTION:A constant current source TRT7 is controlled with a control voltage Vr2 from a control voltage generating circuit BS2. When a current amplification factor beta of a TRT12 of the circuit BS2 is lowered, a base current is reduced, a voltage drop across a resistor R1 is decresed accompanied with the reduction in the collector current and the voltage Vr2 is increased. Thus, a current flowing to a readout reference voltage resistor RR is increased and a readout reference voltage VR is compulsively lowered more than the lowering accompanied with the lowering of the amplification factor beta according to the resistance value of a resistor R4. As a result, the reduction in the readout margin of a memory cell MC consisting of FF comprising TRs T1 and T2 and of a load resistor RL due to the reduction in the amplification factor is suppressed, allowing to achieve constant readout margin independently of temperature change and performance dispersion of components.
JP56034242A 1981-03-10 1981-03-10 Semiconductor memory Pending JPS57150187A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56034242A JPS57150187A (en) 1981-03-10 1981-03-10 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56034242A JPS57150187A (en) 1981-03-10 1981-03-10 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPS57150187A true JPS57150187A (en) 1982-09-16

Family

ID=12408683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56034242A Pending JPS57150187A (en) 1981-03-10 1981-03-10 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS57150187A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456678B2 (en) 2006-10-10 2008-11-25 Atmel Corporation Apparatus and method for providing a temperature compensated reference current

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456678B2 (en) 2006-10-10 2008-11-25 Atmel Corporation Apparatus and method for providing a temperature compensated reference current

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