JPS5714941A - Data input requesting circuit - Google Patents

Data input requesting circuit

Info

Publication number
JPS5714941A
JPS5714941A JP8879980A JP8879980A JPS5714941A JP S5714941 A JPS5714941 A JP S5714941A JP 8879980 A JP8879980 A JP 8879980A JP 8879980 A JP8879980 A JP 8879980A JP S5714941 A JPS5714941 A JP S5714941A
Authority
JP
Japan
Prior art keywords
information
code
processor
given
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8879980A
Other languages
Japanese (ja)
Inventor
Kensuke Uehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8879980A priority Critical patent/JPS5714941A/en
Publication of JPS5714941A publication Critical patent/JPS5714941A/en
Pending legal-status Critical Current

Links

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To accelerate the input request timing for the subsequent data to be delivered to a processor, by invalidating the delaying action of a delaying circuit based on the CR code and then the LF code in case no hard copy device is used.
CONSTITUTION: A display device 15 performs simultaneously both the display and the print based on the common information given from a processor 11. In addition to such device 15, a hard copy device 16 is provided. Then a special delay 17 is given to the input request timing of the subsequent information to be given to the processor 11 in case the information is equal to the CR or LF code. At the same time, the working of a delaying means 17 is invalidated based on the signal showing an unused state of the device 16. Thus the subsequent output pattern information is equally delivered with the similar delay time to the pattern information except the CR and LF codes and regardless of the output pattern information. This enables the display device 15 to perform a high-speed display.
COPYRIGHT: (C)1982,JPO&Japio
JP8879980A 1980-06-30 1980-06-30 Data input requesting circuit Pending JPS5714941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8879980A JPS5714941A (en) 1980-06-30 1980-06-30 Data input requesting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8879980A JPS5714941A (en) 1980-06-30 1980-06-30 Data input requesting circuit

Publications (1)

Publication Number Publication Date
JPS5714941A true JPS5714941A (en) 1982-01-26

Family

ID=13952903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8879980A Pending JPS5714941A (en) 1980-06-30 1980-06-30 Data input requesting circuit

Country Status (1)

Country Link
JP (1) JPS5714941A (en)

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