JPS57146366A - Data transfer system - Google Patents
Data transfer systemInfo
- Publication number
- JPS57146366A JPS57146366A JP56031277A JP3127781A JPS57146366A JP S57146366 A JPS57146366 A JP S57146366A JP 56031277 A JP56031277 A JP 56031277A JP 3127781 A JP3127781 A JP 3127781A JP S57146366 A JPS57146366 A JP S57146366A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- transmission
- interruption
- status
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To prevent the competition of mutual transmission requests, by transmitting and receiving data through the confirmation of status by the end of transmission with an interrupting start from a transmission request and operating a transmission side with an interruption inhibiting state during that time. CONSTITUTION:When a transmission start section is called with a main program of a data transfer controller 1A, an interruption inhibiting signal (a) is immediately transmitted to a controller 2A, and a transmission interrupting signal (a) is transmitted to a processor B and the device 1A waits for a status from the B. In the B, the signal (a) from a processor A is inputted to an interruption controller 2B as a signal c detected at an interruption detector 3B. The device 2B outputs a reception start signal d. A data transfer controller 1B calls a reception start section with a signal d. When an interruption branch is made to the reception start section, the receptionable state is given to the A side via a path g with a signal f. The A judges that a status signal h from th B is possible for transmission, outputs a signal b to a data output device 4A and the data are transmitted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56031277A JPS57146366A (en) | 1981-03-06 | 1981-03-06 | Data transfer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56031277A JPS57146366A (en) | 1981-03-06 | 1981-03-06 | Data transfer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57146366A true JPS57146366A (en) | 1982-09-09 |
Family
ID=12326822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56031277A Pending JPS57146366A (en) | 1981-03-06 | 1981-03-06 | Data transfer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57146366A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59158422A (en) * | 1983-03-01 | 1984-09-07 | Nippon Telegr & Teleph Corp <Ntt> | Information transfer and control system |
-
1981
- 1981-03-06 JP JP56031277A patent/JPS57146366A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59158422A (en) * | 1983-03-01 | 1984-09-07 | Nippon Telegr & Teleph Corp <Ntt> | Information transfer and control system |
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