JPS57145461A - Communication control system - Google Patents
Communication control systemInfo
- Publication number
- JPS57145461A JPS57145461A JP56031548A JP3154881A JPS57145461A JP S57145461 A JPS57145461 A JP S57145461A JP 56031548 A JP56031548 A JP 56031548A JP 3154881 A JP3154881 A JP 3154881A JP S57145461 A JPS57145461 A JP S57145461A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- data
- processor
- constitution
- real time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L13/00—Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To transmit both the real time data and the general data to the same circuit in the same procedure, by transmitting the real time data to which the instantaneous properties is required by means of a UI (unnumbered information) frame and transmitting the general data in the residual idle time via an I frame. CONSTITUTION:When the signal of a certain period T is applied from a period signal producing circuit 2, a processor 1 reads the real time data stored in a memory 5 and applies it to a series-parallel converting part 7 after having a frame constitution of a UI command/response of the HDLC (high level data link control) procedure. The part 7 transmits this frame and informs this transmission to the processor 1. Then the processor 1 reads the general data out of a memory 3 with application of the frame constitution f an I command/response of the HDLC procedure and then applies the data to the part 7. The part 7 transmits this I frame. With repetition of the above-mentioned action, the UI frame is delivered onto the circuit in the period T, and the I frame is delivered in the residual idle time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56031548A JPS57145461A (en) | 1981-03-05 | 1981-03-05 | Communication control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56031548A JPS57145461A (en) | 1981-03-05 | 1981-03-05 | Communication control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57145461A true JPS57145461A (en) | 1982-09-08 |
Family
ID=12334236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56031548A Pending JPS57145461A (en) | 1981-03-05 | 1981-03-05 | Communication control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57145461A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02214398A (en) * | 1989-02-15 | 1990-08-27 | Toshiba Corp | Remote monitor controller |
-
1981
- 1981-03-05 JP JP56031548A patent/JPS57145461A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02214398A (en) * | 1989-02-15 | 1990-08-27 | Toshiba Corp | Remote monitor controller |
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