JPS57137945A - Advance control system of general purpose register - Google Patents
Advance control system of general purpose registerInfo
- Publication number
- JPS57137945A JPS57137945A JP2379781A JP2379781A JPS57137945A JP S57137945 A JPS57137945 A JP S57137945A JP 2379781 A JP2379781 A JP 2379781A JP 2379781 A JP2379781 A JP 2379781A JP S57137945 A JPS57137945 A JP S57137945A
- Authority
- JP
- Japan
- Prior art keywords
- address
- circuit
- generating circuit
- output
- general purpose
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003111 delayed effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Abstract
PURPOSE:To get rid of a dead machine cycle, and to process an instruction efficiently, by selecting an output of an address generating circuit, and controlling a general purpose register. CONSTITUTION:The second address generating circuit 20 receives an output of an instruction decoding circuit 8, generates an address and inputs it to a comparing circuit 24 and an address selecting circuit 22. An output address of the first address generating circuit 10 is also inputted to the comparing circuit 24 and the address selecting circuit 22. The output address of the address generating circuit 10 is inputted to the address selecting circuit 22 through the third address generating circuit 21. This input signal is delayed by a constant interval of time from the output of the first address generating circuit 10. To the address selecting circuit 22, the outputs of each address generating circuit 10, 20 and 21 are inputted. The address selecting circuit 22 selects outputs of 3 kinds and drives a general purpose register 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2379781A JPS57137945A (en) | 1981-02-20 | 1981-02-20 | Advance control system of general purpose register |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2379781A JPS57137945A (en) | 1981-02-20 | 1981-02-20 | Advance control system of general purpose register |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57137945A true JPS57137945A (en) | 1982-08-25 |
JPS6126694B2 JPS6126694B2 (en) | 1986-06-21 |
Family
ID=12120308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2379781A Granted JPS57137945A (en) | 1981-02-20 | 1981-02-20 | Advance control system of general purpose register |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57137945A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6337499U (en) * | 1986-08-29 | 1988-03-10 |
-
1981
- 1981-02-20 JP JP2379781A patent/JPS57137945A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6126694B2 (en) | 1986-06-21 |
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