JPS57134706A - Program selection controller - Google Patents

Program selection controller

Info

Publication number
JPS57134706A
JPS57134706A JP1931881A JP1931881A JPS57134706A JP S57134706 A JPS57134706 A JP S57134706A JP 1931881 A JP1931881 A JP 1931881A JP 1931881 A JP1931881 A JP 1931881A JP S57134706 A JPS57134706 A JP S57134706A
Authority
JP
Japan
Prior art keywords
stored
data
program
resistor
executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1931881A
Other languages
Japanese (ja)
Inventor
Shinichi Yuda
Takao Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1931881A priority Critical patent/JPS57134706A/en
Publication of JPS57134706A publication Critical patent/JPS57134706A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs

Abstract

PURPOSE:To increase the reliability of program change and to reduce the on-line operation stop period for functions outside the objective of change, by storing a specified discrimination data with a removable storage element storing the control program. CONSTITUTION:A plurality of control programs which are arbitrarily selected and executed, are stored in a plurality of removable storage elements 19, 20 and a specified discrimination data is stored in the specific address of the elements. The content of the specific address of a plurality of above-mentioned storage elements is sequentially detected to discriminate the propriety of the execution of the program stored in each storage element through the presence or absence of the specified discrimination data. For example, a resistor 18 is taken as a pull-up resistor and a value of ''O'' for all bits is stored in the head address of an ROM chip 19. At the step 21, the data of the head address is picked up and the discrimination of data is made in the step 22, and when ''O'', i.e. the ROM chip 19 is mounted, the program stored on and after the said ROM is executed.
JP1931881A 1981-02-12 1981-02-12 Program selection controller Pending JPS57134706A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1931881A JPS57134706A (en) 1981-02-12 1981-02-12 Program selection controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1931881A JPS57134706A (en) 1981-02-12 1981-02-12 Program selection controller

Publications (1)

Publication Number Publication Date
JPS57134706A true JPS57134706A (en) 1982-08-20

Family

ID=11996050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1931881A Pending JPS57134706A (en) 1981-02-12 1981-02-12 Program selection controller

Country Status (1)

Country Link
JP (1) JPS57134706A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114602A (en) * 1982-12-22 1984-07-02 Toshiba Corp Programmable controller
JPS6116302A (en) * 1984-05-25 1986-01-24 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Functional controller for automobile
JPS6252609A (en) * 1985-09-02 1987-03-07 Fanuc Ltd Numerical control method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114602A (en) * 1982-12-22 1984-07-02 Toshiba Corp Programmable controller
JPH0410081B2 (en) * 1982-12-22 1992-02-24
JPS6116302A (en) * 1984-05-25 1986-01-24 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Functional controller for automobile
JPS6252609A (en) * 1985-09-02 1987-03-07 Fanuc Ltd Numerical control method

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