JPS57133632A - Electron beam exposing method - Google Patents

Electron beam exposing method

Info

Publication number
JPS57133632A
JPS57133632A JP1945181A JP1945181A JPS57133632A JP S57133632 A JPS57133632 A JP S57133632A JP 1945181 A JP1945181 A JP 1945181A JP 1945181 A JP1945181 A JP 1945181A JP S57133632 A JPS57133632 A JP S57133632A
Authority
JP
Japan
Prior art keywords
controller
matrix
memorized
divided
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1945181A
Other languages
Japanese (ja)
Inventor
Sakae Miyauchi
Kunio Takeuchi
Itsuo Yamamoto
Kaoru Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jeol Ltd
Original Assignee
Jeol Ltd
Nihon Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jeol Ltd, Nihon Denshi KK filed Critical Jeol Ltd
Priority to JP1945181A priority Critical patent/JPS57133632A/en
Publication of JPS57133632A publication Critical patent/JPS57133632A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To equalize the amount of exposure for patterning by a method wherein the patterning to be drawn is divided in matrix-formed microscopic regions and memorized in a memory storage, the ridge point indicating data are successively read out, an exposure process is performed making no overlapping section of exposure using said data. CONSTITUTION:An electron beam exposing device consists of a CPU1, a bit matrix expansion controller 2, a memory controller 3, a bit matrix 4 and a resistors r1-r7. With the above constitution, first, a clear signal is sent to the controller 3 from the CPU1, and the information to be memorized is set in the matrix 4 by the controller 3. At this time, the pattern to be memorized is divided into a number of small regions which will be used as ridge point indicating data, and the patterns divided into small regions should not be overlapped. Subsequently, the signal is expanded to the controller 2 through the intermediaries of the resistors r1-r7, and an exposure process is performed based on this bit matrix.
JP1945181A 1981-02-12 1981-02-12 Electron beam exposing method Pending JPS57133632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1945181A JPS57133632A (en) 1981-02-12 1981-02-12 Electron beam exposing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1945181A JPS57133632A (en) 1981-02-12 1981-02-12 Electron beam exposing method

Publications (1)

Publication Number Publication Date
JPS57133632A true JPS57133632A (en) 1982-08-18

Family

ID=11999671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1945181A Pending JPS57133632A (en) 1981-02-12 1981-02-12 Electron beam exposing method

Country Status (1)

Country Link
JP (1) JPS57133632A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6431418A (en) * 1987-07-28 1989-02-01 Toshiba Machine Co Ltd Charged particle beam lithography equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56115535A (en) * 1980-02-18 1981-09-10 Chiyou Lsi Gijutsu Kenkyu Kumiai Electron beam exposure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56115535A (en) * 1980-02-18 1981-09-10 Chiyou Lsi Gijutsu Kenkyu Kumiai Electron beam exposure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6431418A (en) * 1987-07-28 1989-02-01 Toshiba Machine Co Ltd Charged particle beam lithography equipment

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