JPS57125538A - Synchronizing system for relay line between satellites - Google Patents
Synchronizing system for relay line between satellitesInfo
- Publication number
- JPS57125538A JPS57125538A JP56010886A JP1088681A JPS57125538A JP S57125538 A JPS57125538 A JP S57125538A JP 56010886 A JP56010886 A JP 56010886A JP 1088681 A JP1088681 A JP 1088681A JP S57125538 A JPS57125538 A JP S57125538A
- Authority
- JP
- Japan
- Prior art keywords
- timing
- circuit
- delay
- satellites
- relay line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/204—Multiple access
- H04B7/2046—SS-TDMA, TDMA satellite switching
Abstract
PURPOSE:To synchronize a relay line between satellites and an earth line, by controlling the amount of delay in a delay circuit so that an output timing of a reception timing detector and a reference timing have a specified relation. CONSTITUTION:After a TDMA signal from a satellite is received at a relay line reception antenna 24 between satellites and a receiver 34, the signal is given to a delay circuit 63. At the same time, a reception signal is guided to a frame timing detection circuit 65, and a TDMA frame start timing t1, by detecting a unique word included in a reference burst 18 located at the head of a TDMA frame, for example. This TDMA frame start timing t1 is compared with a switcing timing t0 or t2 formed at a switch control circuit 62 operated as a reference timing generating circuit generating the reference timing of the satellite with a delay amount control circuit 64. Thus, control is made at a delay amount controlling circuit 64 so that the t1 is coincident with the switching timing t2 at a dynamic switch matrix 61.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56010886A JPS57125538A (en) | 1981-01-29 | 1981-01-29 | Synchronizing system for relay line between satellites |
US06/343,181 US4456988A (en) | 1981-01-29 | 1982-01-27 | Satellite repeater |
DE19823202656 DE3202656A1 (en) | 1981-01-29 | 1982-01-28 | SATELLITE RELAY STATION |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56010886A JPS57125538A (en) | 1981-01-29 | 1981-01-29 | Synchronizing system for relay line between satellites |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57125538A true JPS57125538A (en) | 1982-08-04 |
JPS6335136B2 JPS6335136B2 (en) | 1988-07-13 |
Family
ID=11762791
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56010886A Granted JPS57125538A (en) | 1981-01-29 | 1981-01-29 | Synchronizing system for relay line between satellites |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57125538A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002524963A (en) * | 1998-09-09 | 2002-08-06 | クゥアルコム・インコーポレイテッド | User terminal clock error measurement and correction system and method |
-
1981
- 1981-01-29 JP JP56010886A patent/JPS57125538A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002524963A (en) * | 1998-09-09 | 2002-08-06 | クゥアルコム・インコーポレイテッド | User terminal clock error measurement and correction system and method |
Also Published As
Publication number | Publication date |
---|---|
JPS6335136B2 (en) | 1988-07-13 |
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