JPS57123592A - Accepting device for storage access - Google Patents
Accepting device for storage accessInfo
- Publication number
- JPS57123592A JPS57123592A JP56008925A JP892581A JPS57123592A JP S57123592 A JPS57123592 A JP S57123592A JP 56008925 A JP56008925 A JP 56008925A JP 892581 A JP892581 A JP 892581A JP S57123592 A JPS57123592 A JP S57123592A
- Authority
- JP
- Japan
- Prior art keywords
- refreshment
- signal
- time
- processor
- acceptance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To minimize the influence of refreshment upon another device, such as a processor, by varying the acceptance priority level of a refreshment access request with time and by inhibiting a refreshment access request for a constant time. CONSTITUTION:The delay circuit 15 of a priority circuit 1 delays a processor access acceptance inhibition signal 161 by time TW behind a refreshment access signal 103, so the access request signal 101 of a processor P has priority to the signal 103. Similarly, the signal 101, an access request signal 102 from a processor Q, and the signal 103 are accepted preferentially in this order in the time TW and the signals 103, 101 and 102 are accepted in order after the time TW. During two machine cycles of the time TW after the FF24 of an acceptance detecting circuit 2 is set by timing signals 104, 105 and 201 in every machine cycle, a refreshment acceptance inhibition signal 171 goes down to a 0 to inhibit the acceptance of refreshment. Consequently, the influence of refreshment upon a device such as the processor is minimized.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56008925A JPS57123592A (en) | 1981-01-26 | 1981-01-26 | Accepting device for storage access |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56008925A JPS57123592A (en) | 1981-01-26 | 1981-01-26 | Accepting device for storage access |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57123592A true JPS57123592A (en) | 1982-08-02 |
JPH0146960B2 JPH0146960B2 (en) | 1989-10-11 |
Family
ID=11706226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56008925A Granted JPS57123592A (en) | 1981-01-26 | 1981-01-26 | Accepting device for storage access |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57123592A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6242394A (en) * | 1985-08-20 | 1987-02-24 | Fujitsu Ltd | Refresh system for memory |
-
1981
- 1981-01-26 JP JP56008925A patent/JPS57123592A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6242394A (en) * | 1985-08-20 | 1987-02-24 | Fujitsu Ltd | Refresh system for memory |
Also Published As
Publication number | Publication date |
---|---|
JPH0146960B2 (en) | 1989-10-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5399736A (en) | Semiconductor memory unit | |
JPS5353386A (en) | Time difference detection circuit | |
JPS57123592A (en) | Accepting device for storage access | |
FR2360937A1 (en) | EXTENSION AND HOLDING RHYTHM CIRCUIT | |
JPS57123591A (en) | Accepting device for storage access | |
JPS5314238A (en) | Electronic ignition system | |
JPS5415620A (en) | Buffer memory unit | |
ES8405158A1 (en) | Process and device for detecting frequency variations. | |
JPS5440049A (en) | Information process system | |
JPS5440054A (en) | Information process system | |
JPS5434640A (en) | Memory unit | |
JPS5323552A (en) | Pulse row detection circuit | |
JPS5383543A (en) | Microprogram control unit | |
JPS56145587A (en) | Selective control circuit of dynamic memory | |
JPS5410810A (en) | Tester for electronic controller of automobile | |
JPS524136A (en) | Bus connection device | |
JPS5313477A (en) | Operating time measuring system for mechanism | |
JPS5658185A (en) | Buffer memory control device | |
JPS5461760A (en) | Controlling of sorter | |
JPS5264846A (en) | Unit selection system | |
JPS56143036A (en) | Response synchronizing system | |
JPS5733489A (en) | Dynamic semiconductor storage device | |
JPS5244697A (en) | Automatic vending machine | |
JPS5436143A (en) | Data processor | |
JPS52144935A (en) | Detecting circuit for priority processing request word position |