JPS57116484A - Multiscreen display television receiver - Google Patents

Multiscreen display television receiver

Info

Publication number
JPS57116484A
JPS57116484A JP197481A JP197481A JPS57116484A JP S57116484 A JPS57116484 A JP S57116484A JP 197481 A JP197481 A JP 197481A JP 197481 A JP197481 A JP 197481A JP S57116484 A JPS57116484 A JP S57116484A
Authority
JP
Japan
Prior art keywords
memory
data
tuners
channel
specified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP197481A
Other languages
Japanese (ja)
Inventor
Akinobu Okazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP197481A priority Critical patent/JPS57116484A/en
Publication of JPS57116484A publication Critical patent/JPS57116484A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To improve the operability of a multiscreen display TV receiver by automatically switching channels by presetting a desired channel and the time when the channel is received. CONSTITUTION:Video chrominance-signal processing circuits 14A-14D process output signals from tuners 13A-13D to display TV signals, received by the tuners 13A-13D, on an image receiving tube. A switching data memory 31 store channel data for specifying the tuners 13A-13D inputted through operation on a keyboard 37 and time data for the reception of them in pairs, and the time data stored in the memory 31 and current-time data generated by a timer circuit 33 are compared mutually by a comparator 32. When the comparator 32 generates a coincident output, the specified tuner data and specified channel data stored in the memory 31 is read on the basis of the address of an address memory 35 and channels of the specified tuners 13A-13D are selected through a decoder 35 to display chrominance signal data from memory circuits 15A-16B.
JP197481A 1981-01-09 1981-01-09 Multiscreen display television receiver Pending JPS57116484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP197481A JPS57116484A (en) 1981-01-09 1981-01-09 Multiscreen display television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP197481A JPS57116484A (en) 1981-01-09 1981-01-09 Multiscreen display television receiver

Publications (1)

Publication Number Publication Date
JPS57116484A true JPS57116484A (en) 1982-07-20

Family

ID=11516521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP197481A Pending JPS57116484A (en) 1981-01-09 1981-01-09 Multiscreen display television receiver

Country Status (1)

Country Link
JP (1) JPS57116484A (en)

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