JPS57113159A - Operation stop system of processor - Google Patents

Operation stop system of processor

Info

Publication number
JPS57113159A
JPS57113159A JP55188271A JP18827180A JPS57113159A JP S57113159 A JPS57113159 A JP S57113159A JP 55188271 A JP55188271 A JP 55188271A JP 18827180 A JP18827180 A JP 18827180A JP S57113159 A JPS57113159 A JP S57113159A
Authority
JP
Japan
Prior art keywords
register
access
value
address
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55188271A
Other languages
Japanese (ja)
Inventor
Toshio Oma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55188271A priority Critical patent/JPS57113159A/en
Publication of JPS57113159A publication Critical patent/JPS57113159A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To reduce a waste of start time by decreasing a prescribed frequency of access from a set value when accessing the same address more than once and by stopping a processing system when the frequency reaches zero. CONSTITUTION:A memory address register MAR, an address stop register ASR, and an access-frequency specifying register CTR are set and access is started. When the register MAR and address top register ASR has the same value and a coincidence circuit CIN outputs a coincidence signal, a -1 subtraction processing circuit subtracts one from the value of the access-frequency specifying register CTR and adds one to the value of the register MAR. Then, the access-frequency specifying register CTR goes down to zero, a stop signal is outputted to stop a processing system device.
JP55188271A 1980-12-29 1980-12-29 Operation stop system of processor Pending JPS57113159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188271A JPS57113159A (en) 1980-12-29 1980-12-29 Operation stop system of processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188271A JPS57113159A (en) 1980-12-29 1980-12-29 Operation stop system of processor

Publications (1)

Publication Number Publication Date
JPS57113159A true JPS57113159A (en) 1982-07-14

Family

ID=16220744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188271A Pending JPS57113159A (en) 1980-12-29 1980-12-29 Operation stop system of processor

Country Status (1)

Country Link
JP (1) JPS57113159A (en)

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