JPS57109062A - Error processing system - Google Patents

Error processing system

Info

Publication number
JPS57109062A
JPS57109062A JP55186811A JP18681180A JPS57109062A JP S57109062 A JPS57109062 A JP S57109062A JP 55186811 A JP55186811 A JP 55186811A JP 18681180 A JP18681180 A JP 18681180A JP S57109062 A JPS57109062 A JP S57109062A
Authority
JP
Japan
Prior art keywords
error
cpu
chp
sent
msu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55186811A
Other languages
Japanese (ja)
Other versions
JPS6058491B2 (en
Inventor
Terutaka Tateishi
Minoru Etsuno
Kazuyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55186811A priority Critical patent/JPS6058491B2/en
Publication of JPS57109062A publication Critical patent/JPS57109062A/en
Publication of JPS6058491B2 publication Critical patent/JPS6058491B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To classify errors through the software of a CPU and to reconstitute a system, by informing a request origin that an error is detected by a storage controller, and also reporting the detection and its address to the CPU. CONSTITUTION:An access request from a CPU or channel controller CHP is analyzed by the access control circuit 18 of a storage controller, and request information is sent to a storage device MSU through a register 12. A read and a write request from the CPU or CHP are selected by the selecting circuits 19 and 20 of the cntroller respectively and sent to the MSU through registers 13 and 14. When error information M3 is sent from the MSU, the information M3 and read data M4 are applied to registers 16 and 17, and an error detecting circuit 21 discriminates the data M4. When an error is discriminated through said discrimination, the CHP is informed that the error is detected, and the CPU is informed of the error M3 and its error address M5.
JP55186811A 1980-12-26 1980-12-26 Error processing method Expired JPS6058491B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55186811A JPS6058491B2 (en) 1980-12-26 1980-12-26 Error processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55186811A JPS6058491B2 (en) 1980-12-26 1980-12-26 Error processing method

Publications (2)

Publication Number Publication Date
JPS57109062A true JPS57109062A (en) 1982-07-07
JPS6058491B2 JPS6058491B2 (en) 1985-12-20

Family

ID=16194999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55186811A Expired JPS6058491B2 (en) 1980-12-26 1980-12-26 Error processing method

Country Status (1)

Country Link
JP (1) JPS6058491B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60207986A (en) * 1984-04-02 1985-10-19 Toshiba Corp Data processing system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM SYSTEM PRIRCIPLES OF OPERATION=1980 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60207986A (en) * 1984-04-02 1985-10-19 Toshiba Corp Data processing system

Also Published As

Publication number Publication date
JPS6058491B2 (en) 1985-12-20

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