JPS57109041A - Data transfer controlling system - Google Patents
Data transfer controlling systemInfo
- Publication number
- JPS57109041A JPS57109041A JP55186903A JP18690380A JPS57109041A JP S57109041 A JPS57109041 A JP S57109041A JP 55186903 A JP55186903 A JP 55186903A JP 18690380 A JP18690380 A JP 18690380A JP S57109041 A JPS57109041 A JP S57109041A
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- instruction
- data
- equipment
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Abstract
PURPOSE:To improve circuit processing efficiency by providing the 1st buffer, the 2nd buffer which has greater capacity, a processor, etc., to a data transfer controlling system which controls transmitted and received data by a circuit controller. CONSTITUTION:When an instruction code, e.g., c3 is sent from a processor 1 to a terminal equipment 9, a processing part 6 stores the code c3 in a buffer b3 and then sends it from a transmission part 8 to the equipment 9. When buffers B1-Bm are used in transmitting an instruction c2 and data d2 by the processor 1, the instruction c2 is stored in a buffer b2. Then when the procesing part 6 detects the buffer B2 being empty, the data d2 of a main storage device is stored in the buffer B2 and the instruction c2 is transferred to the buffer B2. The processing part 6 sends the instruction c2 and data d2 to the equipment 9 through the transmission part 8. On the other hand, when circuit information from the equipment is present, a circuit controller 4 discriminates the information and when it is an instruction code c1, transfer from the buffer B1 to the buffer b1 is performed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55186903A JPS6029987B2 (en) | 1980-12-26 | 1980-12-26 | Data transfer control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55186903A JPS6029987B2 (en) | 1980-12-26 | 1980-12-26 | Data transfer control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57109041A true JPS57109041A (en) | 1982-07-07 |
JPS6029987B2 JPS6029987B2 (en) | 1985-07-13 |
Family
ID=16196692
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55186903A Expired JPS6029987B2 (en) | 1980-12-26 | 1980-12-26 | Data transfer control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6029987B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63132551A (en) * | 1986-11-25 | 1988-06-04 | Oki Electric Ind Co Ltd | Communication control unit |
-
1980
- 1980-12-26 JP JP55186903A patent/JPS6029987B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63132551A (en) * | 1986-11-25 | 1988-06-04 | Oki Electric Ind Co Ltd | Communication control unit |
JPH0744577B2 (en) * | 1986-11-25 | 1995-05-15 | 沖電気工業株式会社 | Communication control device |
Also Published As
Publication number | Publication date |
---|---|
JPS6029987B2 (en) | 1985-07-13 |
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