JPS5710834A - Communication controlling system - Google Patents

Communication controlling system

Info

Publication number
JPS5710834A
JPS5710834A JP8535080A JP8535080A JPS5710834A JP S5710834 A JPS5710834 A JP S5710834A JP 8535080 A JP8535080 A JP 8535080A JP 8535080 A JP8535080 A JP 8535080A JP S5710834 A JPS5710834 A JP S5710834A
Authority
JP
Japan
Prior art keywords
incoming
processor
autonomously
sends
communication controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8535080A
Other languages
Japanese (ja)
Other versions
JPS5953575B2 (en
Inventor
Yukinori Inoue
Yasuhiro Nakahara
Hiroo Mizuguchi
Toshiyuki Odakawa
Kanji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55085350A priority Critical patent/JPS5953575B2/en
Publication of JPS5710834A publication Critical patent/JPS5710834A/en
Publication of JPS5953575B2 publication Critical patent/JPS5953575B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To reduce an interruption to a processor by constituting so that a communication controller sends an incoming reject signal or a controlled not ready signal autonomously, in a station system which is equipped with the processor and the communication controller. CONSTITUTION:When it has been informed by an incoming reject command 7 from a processor 4 that incoming is impossible against outgoing from other terminal, a communication controller 3 sends out an end interruption according to the incoming reject command immediately, to the processor device 4, and also thereafter, sends the incoming reject signal autonomously at every incoming from other terminal. Or, in this case, it autonomously sends a controlled not ready signal continuously. These transmissions are executed autonomously until an incoming receive command 8 is issued from the processing device, and an interruption to the processor 4 is reduced.
JP55085350A 1980-06-24 1980-06-24 Communication control method Expired JPS5953575B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55085350A JPS5953575B2 (en) 1980-06-24 1980-06-24 Communication control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55085350A JPS5953575B2 (en) 1980-06-24 1980-06-24 Communication control method

Publications (2)

Publication Number Publication Date
JPS5710834A true JPS5710834A (en) 1982-01-20
JPS5953575B2 JPS5953575B2 (en) 1984-12-26

Family

ID=13856224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55085350A Expired JPS5953575B2 (en) 1980-06-24 1980-06-24 Communication control method

Country Status (1)

Country Link
JP (1) JPS5953575B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230749A (en) * 1984-04-28 1985-11-16 Fujitsu Ltd Response controlling system of circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230749A (en) * 1984-04-28 1985-11-16 Fujitsu Ltd Response controlling system of circuit

Also Published As

Publication number Publication date
JPS5953575B2 (en) 1984-12-26

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