JPS57106932A - Determination system for multiple terminal constitution - Google Patents

Determination system for multiple terminal constitution

Info

Publication number
JPS57106932A
JPS57106932A JP55183081A JP18308180A JPS57106932A JP S57106932 A JPS57106932 A JP S57106932A JP 55183081 A JP55183081 A JP 55183081A JP 18308180 A JP18308180 A JP 18308180A JP S57106932 A JPS57106932 A JP S57106932A
Authority
JP
Japan
Prior art keywords
terminal
constitution
serial number
type
multiple terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55183081A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Iwanaga
Takanao Hiraoka
Hiroichi Suzuki
Yasutomo Uenishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55183081A priority Critical patent/JPS57106932A/en
Publication of JPS57106932A publication Critical patent/JPS57106932A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To specify multiple terminal constitution automatically by storing the key of system information on the multiple terminal constitution in each terminal of the multiple terminal constitution, and by registering the key in the table of a terminal controller when the terminal is started. CONSTITUTION:In respective terminals T1-T3 forming multiple terminal constitution, serial numbers #0-#2 of multiple terminals WS, a WS type number indicating the number of WSs, and characteristic keys K1-K3 including series numbers in the WSs are stored. For example, when the terminal T1 is started, the WS serial number #0, WS type #2, and in-WS serial number #0 are registerd in the table TBL of a terminal controller T/C, and this WS is found to be a two- terminal type by the WS type #2, thereby waiting for the WS serial number #1. Therefore, when the terminal T2 is started and the WS serial number #0 and in-WS serial number#1 are registered in the TBL, the multiple terminal constitutionis completed and communication with a host H/C is enabled. Thus, the tape having the function of switching between the host and terminals is generated automatically, and the simle means specifies the WS constitution in the T/C, modifying the system conveniently.
JP55183081A 1980-12-24 1980-12-24 Determination system for multiple terminal constitution Pending JPS57106932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55183081A JPS57106932A (en) 1980-12-24 1980-12-24 Determination system for multiple terminal constitution

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55183081A JPS57106932A (en) 1980-12-24 1980-12-24 Determination system for multiple terminal constitution

Publications (1)

Publication Number Publication Date
JPS57106932A true JPS57106932A (en) 1982-07-03

Family

ID=16129421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55183081A Pending JPS57106932A (en) 1980-12-24 1980-12-24 Determination system for multiple terminal constitution

Country Status (1)

Country Link
JP (1) JPS57106932A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984003966A1 (en) * 1983-04-07 1984-10-11 Fanuc Ltd Method of controlling data input/output
WO1984003965A1 (en) * 1983-04-07 1984-10-11 Fanuc Ltd Method of controlling data transfer
JPS6045867A (en) * 1983-08-22 1985-03-12 Fujitsu Ltd Information processor
JPS63155248A (en) * 1986-12-18 1988-06-28 Sharp Corp How to select a computer device interface

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984003966A1 (en) * 1983-04-07 1984-10-11 Fanuc Ltd Method of controlling data input/output
WO1984003965A1 (en) * 1983-04-07 1984-10-11 Fanuc Ltd Method of controlling data transfer
JPS6045867A (en) * 1983-08-22 1985-03-12 Fujitsu Ltd Information processor
JPS63155248A (en) * 1986-12-18 1988-06-28 Sharp Corp How to select a computer device interface

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