JPS57106260A - Loop transmission system - Google Patents
Loop transmission systemInfo
- Publication number
- JPS57106260A JPS57106260A JP55182287A JP18228780A JPS57106260A JP S57106260 A JPS57106260 A JP S57106260A JP 55182287 A JP55182287 A JP 55182287A JP 18228780 A JP18228780 A JP 18228780A JP S57106260 A JPS57106260 A JP S57106260A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- idle pattern
- transmission
- primary station
- station
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To reduce the load of a primary station to simplify the processing for transmission, by converting the transmission signal of the primary station to an idle pattern before leading this signal into the primary station when this signal is returned to the primary station. CONSTITUTION:When a primary station 1 transmits a polling signal by the command from a CPU4, an idle pattern and the transmission signal are supplied to secondary stations 21-23 through a loop transmission line and are taken into prescribed secondary stations corresponding to addresses and are returned to the station 1 through the transmission line. Then, a timer 5 is operated at the transmission start time in the station 1 to switch a switch 6 to the side of an idle pattern generating circuit 7 for a constant time. Thus, the receiving circuit of an LSI 3 is disconnected from the transmission line, and the idle pattern from the circuit 7 is supplied to the receiving circuit. Consequently, the signal returned to stations 21-23 is converted to the idle pattern equivalently.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55182287A JPS57106260A (en) | 1980-12-23 | 1980-12-23 | Loop transmission system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55182287A JPS57106260A (en) | 1980-12-23 | 1980-12-23 | Loop transmission system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57106260A true JPS57106260A (en) | 1982-07-02 |
Family
ID=16115634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55182287A Pending JPS57106260A (en) | 1980-12-23 | 1980-12-23 | Loop transmission system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57106260A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7039051B2 (en) | 1999-08-18 | 2006-05-02 | Fujitsu Limited | Data sending system |
-
1980
- 1980-12-23 JP JP55182287A patent/JPS57106260A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7039051B2 (en) | 1999-08-18 | 2006-05-02 | Fujitsu Limited | Data sending system |
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