JPS5710569B2 - - Google Patents

Info

Publication number
JPS5710569B2
JPS5710569B2 JP3306372A JP3306372A JPS5710569B2 JP S5710569 B2 JPS5710569 B2 JP S5710569B2 JP 3306372 A JP3306372 A JP 3306372A JP 3306372 A JP3306372 A JP 3306372A JP S5710569 B2 JPS5710569 B2 JP S5710569B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3306372A
Other languages
Japanese (ja)
Other versions
JPS48101891A (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3306372A priority Critical patent/JPS5710569B2/ja
Publication of JPS48101891A publication Critical patent/JPS48101891A/ja
Publication of JPS5710569B2 publication Critical patent/JPS5710569B2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP3306372A 1972-03-31 1972-03-31 Expired JPS5710569B2 (en:Method)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3306372A JPS5710569B2 (en:Method) 1972-03-31 1972-03-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3306372A JPS5710569B2 (en:Method) 1972-03-31 1972-03-31

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP56114772A Division JPS57118666A (en) 1981-07-22 1981-07-22 Complementary mos integrated circuit device

Publications (2)

Publication Number Publication Date
JPS48101891A JPS48101891A (en:Method) 1973-12-21
JPS5710569B2 true JPS5710569B2 (en:Method) 1982-02-26

Family

ID=12376264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3306372A Expired JPS5710569B2 (en:Method) 1972-03-31 1972-03-31

Country Status (1)

Country Link
JP (1) JPS5710569B2 (en:Method)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4044454A (en) * 1975-04-16 1977-08-30 Ibm Corporation Method for forming integrated circuit regions defined by recessed dielectric isolation
JPS58115846A (ja) * 1981-12-28 1983-07-09 Matsushita Electric Ind Co Ltd 相補型絶縁ゲ−ト型半導体装置
JPS5955055A (ja) * 1982-09-24 1984-03-29 Fujitsu Ltd 半導体装置の製造方法
JP2597990B2 (ja) * 1986-03-31 1997-04-09 株式会社東芝 相補型半導体装置及びその製造方法
JPS63128659A (ja) * 1986-11-18 1988-06-01 Seiko Epson Corp 半導体装置
JPH0165151U (en:Method) * 1988-09-22 1989-04-26

Also Published As

Publication number Publication date
JPS48101891A (en:Method) 1973-12-21

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