JPS57101948A - Execution time controlling circuit of instruction - Google Patents
Execution time controlling circuit of instructionInfo
- Publication number
- JPS57101948A JPS57101948A JP17919480A JP17919480A JPS57101948A JP S57101948 A JPS57101948 A JP S57101948A JP 17919480 A JP17919480 A JP 17919480A JP 17919480 A JP17919480 A JP 17919480A JP S57101948 A JPS57101948 A JP S57101948A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- inputted
- instruction
- coincidence
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4825—Interrupt from clock, e.g. time of day
Abstract
PURPOSE:To easily confirm an executed instruction and its address, by constituting so that an execution time interval of the instructions can be set optionally. CONSTITUTION:A timing signal generated by a timing generating circuit 1 is inputted to a counting circuit 5. The circuit 5 counts the inputted timing signal and outputs its counting value. The outputted counting value is inputted to a coincidence circuit 6. As for its inputted signal, its coincidence with an instruction execution time interval which has been set by the counting value and a time setting circuit 7 is decided by the coincidence circuit 6. In this case, a reset signal and a coincidence signal are generated from the circuit 6 at every execution time interval. The reset signal is inputted to the circuit 6 and sets the counting value to ''0''. The coincidence signal is inputted to an address generating circuit 2, and this circuit 2 detects an address where an instruction is stored, in accordance with the coincidence signal, and reads out the instruction of its address. Subsequently, this executed instruction and the address are displayed on a displaying circuit 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17919480A JPS57101948A (en) | 1980-12-17 | 1980-12-17 | Execution time controlling circuit of instruction |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17919480A JPS57101948A (en) | 1980-12-17 | 1980-12-17 | Execution time controlling circuit of instruction |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57101948A true JPS57101948A (en) | 1982-06-24 |
Family
ID=16061573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17919480A Pending JPS57101948A (en) | 1980-12-17 | 1980-12-17 | Execution time controlling circuit of instruction |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57101948A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008161781A (en) * | 2006-12-27 | 2008-07-17 | Dkk Toa Corp | Filter unit |
-
1980
- 1980-12-17 JP JP17919480A patent/JPS57101948A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008161781A (en) * | 2006-12-27 | 2008-07-17 | Dkk Toa Corp | Filter unit |
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