JPS5694693A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPS5694693A JPS5694693A JP17069879A JP17069879A JPS5694693A JP S5694693 A JPS5694693 A JP S5694693A JP 17069879 A JP17069879 A JP 17069879A JP 17069879 A JP17069879 A JP 17069879A JP S5694693 A JPS5694693 A JP S5694693A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- printed
- board
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17069879A JPS5694693A (en) | 1979-12-27 | 1979-12-27 | Printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17069879A JPS5694693A (en) | 1979-12-27 | 1979-12-27 | Printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5694693A true JPS5694693A (en) | 1981-07-31 |
Family
ID=15909730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17069879A Pending JPS5694693A (en) | 1979-12-27 | 1979-12-27 | Printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5694693A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6045459U (en) * | 1983-09-06 | 1985-03-30 | 松下電器産業株式会社 | Wiring body for thick film hybrid circuit |
JPS6486525A (en) * | 1987-09-29 | 1989-03-31 | Toshiba Corp | Electronic circuit component |
JP2020178059A (en) * | 2019-04-19 | 2020-10-29 | ハイソル株式会社 | Wire bonding method and semiconductor chip wiring structure |
-
1979
- 1979-12-27 JP JP17069879A patent/JPS5694693A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6045459U (en) * | 1983-09-06 | 1985-03-30 | 松下電器産業株式会社 | Wiring body for thick film hybrid circuit |
JPS6486525A (en) * | 1987-09-29 | 1989-03-31 | Toshiba Corp | Electronic circuit component |
JP2020178059A (en) * | 2019-04-19 | 2020-10-29 | ハイソル株式会社 | Wire bonding method and semiconductor chip wiring structure |
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