JPS5690652A - Circuit connection system - Google Patents

Circuit connection system

Info

Publication number
JPS5690652A
JPS5690652A JP16791179A JP16791179A JPS5690652A JP S5690652 A JPS5690652 A JP S5690652A JP 16791179 A JP16791179 A JP 16791179A JP 16791179 A JP16791179 A JP 16791179A JP S5690652 A JPS5690652 A JP S5690652A
Authority
JP
Japan
Prior art keywords
signals
buffer memory
processor
transmission line
adapters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16791179A
Other languages
Japanese (ja)
Inventor
Akira Takeyama
Akimasa Yatsuhoshi
Akiyoshi Mita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16791179A priority Critical patent/JPS5690652A/en
Publication of JPS5690652A publication Critical patent/JPS5690652A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
    • H04L5/24—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters
    • H04L5/245—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters with a number of discharge tubes or semiconductor elements which successively connect the different channels to the transmission channels

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To reduce overlaps of functions by connecting terminals to a processor by scanning a buffer memory from the processor. CONSTITUTION:Signals from respective terminals 01-05 are received by corresponding circuit adapters 31-35. Multiplexer 36 multiplexes signals from respective adapters 31-35 via multiplex transmission line 126. The signals on transmission line 126 are stored in specific addresses of buffer memory 150 respectively corresponding to respective circuit adapters, and information signals and control signals, adapter by adapter. Processor 40 scans buffer memory 150 to read the respective signals, so that it can receive the information signals and control signals from respective terminals. Multiplexing circuit 36 and buffer memory 150 are installed at a distance via multiplex transmission line 126.
JP16791179A 1979-12-24 1979-12-24 Circuit connection system Pending JPS5690652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16791179A JPS5690652A (en) 1979-12-24 1979-12-24 Circuit connection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16791179A JPS5690652A (en) 1979-12-24 1979-12-24 Circuit connection system

Publications (1)

Publication Number Publication Date
JPS5690652A true JPS5690652A (en) 1981-07-22

Family

ID=15858328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16791179A Pending JPS5690652A (en) 1979-12-24 1979-12-24 Circuit connection system

Country Status (1)

Country Link
JP (1) JPS5690652A (en)

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