JPS5687209A - Digital modulating circuit - Google Patents

Digital modulating circuit

Info

Publication number
JPS5687209A
JPS5687209A JP16295479A JP16295479A JPS5687209A JP S5687209 A JPS5687209 A JP S5687209A JP 16295479 A JP16295479 A JP 16295479A JP 16295479 A JP16295479 A JP 16295479A JP S5687209 A JPS5687209 A JP S5687209A
Authority
JP
Japan
Prior art keywords
bits
pulse
detection pulse
detection
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16295479A
Other languages
Japanese (ja)
Inventor
Masatoshi Shinpo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16295479A priority Critical patent/JPS5687209A/en
Publication of JPS5687209A publication Critical patent/JPS5687209A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To obtain an M2FM modulating circuit that provides high-density recording, by adding a condition circuit to the M2FM modulating circuit.
CONSTITUTION: From NRZ (Non-Return to Zero) type input data, a detection pulse of bit "1" and another detection pulse for a boundrary between bits "0" are generated and the latter pulse is counted is FF, whose output is read by delay D-FF that receives as a clock a pulse having position information in the middle of data bits and equal in period to data bits so that the boundary detection pulse will be in the middle of the D-FF output. Then, FF is cleared with the detection pulse of bit "1" to determine the starting and ending points of continuous bits "0" and when ≤3 bits "0" continue, only odd-numbered detection pulses are extracted to perform logical operation between the detection pulse of bit "1" and the detection pulses for a boundary between odd-numbered bits "0" before NRZI modulation. In the figure, D (DeLay)-FFs are represented as A and H, OR circuits as B, C and I, NAND circuits as D and E, and FFs as G and F.
COPYRIGHT: (C)1981,JPO&Japio
JP16295479A 1979-12-14 1979-12-14 Digital modulating circuit Pending JPS5687209A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16295479A JPS5687209A (en) 1979-12-14 1979-12-14 Digital modulating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16295479A JPS5687209A (en) 1979-12-14 1979-12-14 Digital modulating circuit

Publications (1)

Publication Number Publication Date
JPS5687209A true JPS5687209A (en) 1981-07-15

Family

ID=15764421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16295479A Pending JPS5687209A (en) 1979-12-14 1979-12-14 Digital modulating circuit

Country Status (1)

Country Link
JP (1) JPS5687209A (en)

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